An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

/pdf/analog-circuits-in-ultra-deep-submicron-cmos-1g96qlvoip.pdf

Analog circuits in ultra-deep-submicron CMOS

An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-mum CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8-V supply and occupies an area of only 0.59 mm2

A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

/pdf/noise-modeling-for-rf-cmos-circuit-simulation-16f065ze5x.pdf

Noise modeling for RF CMOS circuit simulation

A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

A model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters. Additionally, the presence of (i) noise associated with avalanche multiplication, and (ii) shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.

/pdf/compact-modeling-of-drain-and-gate-current-noise-for-rf-cmos-4aimr8lawx.pdf

Compact modeling of drain and gate current noise for RF CMOS

We report a single-loop inductor suitable for integration in a differential voltage-controlled oscillator (LC-VCO) with 0.6-nH inductance and record quality factors of 18 at 10 GHz and 20 at 15 GHz fabricated in an industrial CMOS process on a 10 /spl Omega/cm substrate. A new lumped element model which accurately describes the inductor performance without the need for frequency-dependent elements is presented. During the course of this work, we found that a patterned ground shield significantly improves the inductor performance at these frequencies, but only when the polysilicon bars are connected from the center of the inductor.

Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-μm gate-length CMOS

Small-signal S-parameters measured on wafer for conventional NMOS devices with gate lengths ranging from 10 J.Lm down to 0.35 J.Lm have been -used to clarify and model the geometry scaling of the substrate loss resistance for the first time. This fa­ cilitates accurate simulation of the RF be­ haviour in all regions of operation.

http://ieeexplore.ieee.org/iel5/10058/32252/01503593.pdf

Geometry Scaling of the Substrate Loss of RF MOSFETs

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design Existing models underestimate the induced gate noise for short-channel devices In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation The model accurately describes noise without fitting any additional parameters

New compact model for induced gate current noise [MOSFET]

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

/pdf/test-structure-design-considerations-for-rf-cv-measurements-1bgl0y0532.pdf

L.F. Tiemeijer

Papers

Compact modeling of drain and gate current noise for RF CMOS

Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-μm gate-length CMOS

Geometry Scaling of the Substrate Loss of RF MOSFETs

New compact model for induced gate current noise [MOSFET]

Test structure design considerations for RF-CV measurements on leaky dielectrics