This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- ?m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

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A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10 GHz is introduced that achieves a noise figure of 2.9 to 5.7 dB with a power dissipation of 22 mW. Several multi-decade carrier generation techniques are proposed and a CMOS prototype is presented that exhibits a phase noise of -94 to -120 dBc/Hz at 1-MHz offset while consuming 31 mW.

Cognitive Radio Design Challenges and Techniques

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A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.

Study of Subharmonically Injection-Locked PLLs

This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax the generation, division, and distribution of the local oscillator signal are reviewed. Last, integration issues for transmit and receive paths and for multiple beamforming transceivers are addressed.

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Design of Millimeter-Wave CMOS Radios: A Tutorial

The frequency divider (FD) is one of the key components in very-high-frequency (VHF) PLLs. Conventionally, injection-locked frequency divider (ILFD) , Miller frequency divider, and CML static divider are widely used in various applications. Among these dividers, the ILFD has the highest operation frequency, but the locking range is limited. On the other hand, the static FD covers a wide locking range, but its operation frequency is low and the power consumption is usually high. Since a FD connected to a VCO operates at the highest frequency, the power dissipation and the locking range of a VHF FD should be carefully considered. In a PLL, due to the process and temperature variations, the locking range of the ILFD must be several times larger than the tuning range of the VCO. Thus, it is challenging to design a wide locking-range and low-power ILFD in the millimeter-wave applications. To achieve a higher operational frequency for an ILFD, the distributed LC oscillator is adopted. To widen the locking range of an ILFD, the transconductance-enhancement technique is presented. In this paper, two low-power ILFDs have a locking range of 85.1 to 96.3 GHz and 98.9 to 105.2 GHz, respectively.

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $\mu$ m CMOS Technology

A distributed-LC injection-locked frequency divider is proposed. This frequency divider has been realized in 65 nm CMOS technology. The core area is 0.036 mm2. The measured operation range is 93.5~109.4 GHz. Its center frequency is 102 GHz and the locking range is 15.3%. Its power is 5.5 mW from the supply of 1.1 V.

93.5∼109.4GHz CMOS injection-locked frequency divider with 15.3% locking range

A CMOS 44GHz divide-by-4/5 dual-modulus prescaler is presented. The scaled inductive peaking technique and the merged NOR-FF circuits are used to achieve the high-speed, low power and low voltage operation. Fabricated in a 90nm bulk CMOS process, the prescaler with the on-chip VCO operates from 38.7GHz to 44GHz while consuming 45mW from a 1.2V supply. To the authors' knowledge, this prescaler achieves the highest operation frequency up to 44GHz in the published CMOS prescalers.

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

A 508-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented This clock generator has been fabricated in a 013-mum process The measured reference spur is -5988 dBc at 5102 GHz with an input reference frequency of 1993 MHz The area is 093 mm times 1 mm with the on-chip loop filter and pads It dissipates 87 mW without buffers from a 15-V supply

Lan-Chou Cho

Papers

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $\mu$ m CMOS Technology

93.5∼109.4GHz CMOS injection-locked frequency divider with 15.3% locking range

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $\mu$ m CMOS