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Liang Hailian

Researcher at Jiangnan University

Publications -  30
Citations -  205

Liang Hailian is an academic researcher from Jiangnan University. The author has contributed to research in topics: Voltage & Electrostatic discharge. The author has an hindex of 7, co-authored 30 publications receiving 166 citations. Previous affiliations of Liang Hailian include Zhejiang University.

Papers
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High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique

TL;DR: In this article, a ring-resistance-triggered stacked SCR-laterally diffused MOS was verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger voltage and holding voltage.
Journal ArticleDOI

Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

TL;DR: In this paper, a gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated.
Journal ArticleDOI

RC-Embedded LDMOS-SCR With High Holding Current for High-Voltage I/O ESD Protection

TL;DR: In this article, a lateral diffusion MOS-embedded silicon-controlled rectifier with a high holding current (LDMOS-SCR-HHC) is proposed and verified in a 0.25- $\mu\mbox{m}$ 18-V Bipolar-CMOS-DMOS process.
Journal ArticleDOI

Charge Transport in Vertical GaN Schottky Barrier Diodes: A Refined Physical Model for Conductive Dislocations

TL;DR: In this article, the authors investigated the leakage currents in vertical GaN Schottky barrier diodes by measuring the temperature-dependent current-voltage characteristics and showed that the leakage current is primarily governed by dislocation-associated thermionic field emission (TFE).
Patent

High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate

TL;DR: In this paper, a high-voltage ESD (electro-static discharge) protective device triggered by a bidirectional substrate is presented, which can be used for an on-chip IC (integrated circuit) ESD protective circuit and mainly comprises a substrate Psub, a highvoltage deep N trap, a lightly doped P-type drift region, a first highly doped N+ injection region, another P+ injection regions, a second N+, injection Region, a third N+, injecting Region, another N+, injected Region, and a polycrystalline