We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties that simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared with a log-likelihood domain implementation, requires less irregular and smaller memories. This simplification, together with the gains in the metric sorter, lead to $ 56\%$ to $137\%$ higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large block-lengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.

LLR-Based Successive Cancellation List Decoding of Polar Codes

A reflection of our ultimate understanding of a complex system is our ability to control its behavior. Typically, control has multiple prerequisites: It requires an accurate map of the network that governs the interactions between the system's components, a quantitative description of the dynamical laws that govern the temporal behavior of each component, and an ability to influence the state and temporal behavior of a selected subset of the components. With deep roots in nonlinear dynamics and control theory, notions of control and controllability have taken a new life recently in the study of complex networks, inspiring several fundamental questions: What are the control principles of complex systems? How do networks organize themselves to balance control with functionality? To address these here we review recent advances on the controllability and the control of complex networks, exploring the intricate interplay between a system's structure, captured by its network topology, and the dynamical laws that govern the interactions between the components. We match the pertinent mathematical results with empirical findings and applications. We show that uncovering the control principles of complex systems can help us explore and ultimately understand the fundamental laws that govern their behavior.

Control Principles of Complex Networks

The first stretchable energy-harvesting electronic-skin device capable of differentiating and generating energy from various mechanical stimuli, such as normal pressure, lateral strain, bending, and vibration, is presented. A pressure sensitivity of 0.7 kPa(-1) is achieved in the pressure region <1 kPa with power generation of tens of μW cm(-2) from a gentle finger touch.

Stretchable Energy-Harvesting Tactile Electronic Skin Capable of Differentiating Multiple Mechanical Stimuli Modes

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

A recycling amplifier architecture based on the folded cascode transconductance amplifier is described. The proposed amplifier delivers an appreciably enhanced performance over that of the conventional folded. This is achieved by using previously idle devices in the signal path, which results in an enhanced transconductance, gain, and slew rate. Moreover, the input referred noise and offset analyses are included to demonstrate that the proposed modifications have no adverse effects on these design metrics. Transistor-level simulations and experimental results in TSMC 0.18 mum CMOS process confirm the theoretical results. When compared to the conventional folded cascode, and for the same area and power budgets, the proposed amplifier has almost twice the bandwidth (134.2 MHz versus 70.7 MHz) and better than twice the slew rate (94.1 V/mus versus 42.1 V/mus) while driving the same 5.6 pF load. Also a gain enhancement of 7.6 dB is observed.

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 μm standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 μV rms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

The explosive demand in wireless-capable devices, especially with the proliferation of multiple standards, indicates a great opportunity for adoption of wireless technology at a mass-market level. The communication devices of both today and the future will have not only to allow for a variety of applications, supporting the transfer of characters, audio, graphics, and video data, but they will also have to maintain connection with many other devices rather than with a single base station, in a variety of environments. Moreover, to provide various services from different wireless communication standards with higher capacities and higher data-rates, fully integrated and multifunctional wireless devices will be required. Multifunctional circuits and systems can be made profitable by a large scale of integration, elimination of external components, reduction of silicon area, and extensive reuse of resources. Integration of (Bi)CMOS transceiver RF front-end and analog baseband circuits with computing CMOS circuits on the same silicon chip further reduces costs of multifunctional mobile devices. However, as batteries continue to determine the lifetime and size of mobile equipment, further extension of capabilities of wearable and wireless devices will depend critically on the integrated circuits and systems solutions. The demand for multifunctional and multi-mode wireless-capable devices is accompanied by many significant challenges at system, circuit, and technology levels. In the Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications, we are looking for circuits and systems solutions for multiple communication standards. Examples of topics qualifying for the special issue include: • Adaptive radio circuits and systems • Multifunctional multistandard multi-band circuits and systems • Software-defined radio circuits and systems • Cognitive radio circuits and systems • Low-voltage low-power RF and analog circuits for future generations wireless systems • Ultra Wide Band circuits and systems

Ieee transactions on circuits and systems—ii: express briefs

Contents List of Tables List of Figures Symbols and Abbreviations Physical Definitions 1 Introduction 1.1 Motivation 1.2 Outline of the work 2 ADCs in Deep-Submicron CMOS Technologies 2.1 Introduction 2.2 Scaling-Down of CMOS Technologies 2.2.1 Driving Force of the CMOS Scaling-Down 2.2.2 Moving Into Deep-Submicron CMOS Technologies 2.3 Impact of Moving Into Deep-Submicron CMOS to Analog Circuits 2.3.1 Decreased Supply Voltage 2.3.2 Impact on Transistor Intrinsic Gain 2.3.3 Impact on Device Matching 2.3.4 Impact on Device Noise 2.4 ADCs In Deep-Submicron CMOS 2.4.1 Decreased Signal Swing 2.4.2 Degraded Transistor Characteristics 2.4.3 Distortion 2.4.4 Switch Driving 2.4.5 Improved Device Matching 2.4.6 Digital Circuits Advantages 2.5 Conclusion 3 Principle of sigma-delta ADC 3.1 Introduction 3.2 Basic Analog to Digital Conversion 3.3 Oversampling and Noise Shaping 3.3.1 Oversampling 3.3.2 Noise Shaping 3.3.3 sigma-delta modulator 3.3.4 PerformanceMetrics for the sigma-delta ADC 3.4 Traditional sigma-delta ADC Topology 3.4.1 Single-Loop Single-Bit sigma-delta Modulators 3.4.2 Single-Loop Multibit sigma-delta Modulators 3.4.3 Cascaded sigma-delta Modulators 3.5 Conclusion 4 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: Circuit Level Approach 4.1 Introduction 4.2 Low-Voltage Low-Power OTA Design 4.2.1 Gain Enhanced Current Mirror OTA Design 4.2.2 A Test Gain-Enhanced Current Mirror OTA 4.2.3 Implementation and Measurement Results 4.2.4 Two-Stage OTA Design 4.3 Low-Voltage Low-Power sigma-delta ADC Design 4.3.1 Impact of Circuit Nonidealities to sigma-delta ADC Performance 4.3.2 Modulator Topology Selection 4.3.3 OTA Topology Selection 4.3.4 Transistor Biasing 4.3.5 Scaling of Integrators 4.4 A 1-V 140- Wsigma-delta modulator in 90-nm CMOS 4.4.1 Building Block Circuits Design 4.4.2 Implementation 4.4.3 Measurement Results 4.5 Measurements on PSRR and Low-Frequency Noise Floor 4.5.1 Introduction of PSRR 4.5.2 PSRR Measurement Setup 4.5.3 PSRR Measurement Results 4.5.4 Measurement on Low-Frequency Noise Floor 4.6 Conclusion 5 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: System Level Approach 5.1 Introduction 5.2 The Full Feedforward sigma-delta ADC Topology 5.2.1 Single-Loop Single-Bit Full Feedforward sigma-delta Modulators 5.2.2 Single-Loop Multibit Full Feedforward sigma-delta Modulators 5.2.3 Cascaded Full Feedforward sigma-delta Modulators 5.3 Linearity Analysis of sigma-delta ADC 5.3.1 Non-LinearitiesModeling in sigma-delta ADC 5.3.2 Non-Linear OTA Gain Modeling in sigma-delta ADC 5.3.3 Linearity Performance Comparison 5.4 Circuit Implementation of the Full Feedforward sigma-delta Modulator 5.5 A 1.8-V 2-MS/s sigma-delta Modulator in 0.18- m CMOS 5.5.1 Implementation 5.5.2 Measurement results 5.6 A 1-V 1-MS/s sigma-delta Modulator in 0.13- m CMOS 5.6.1 Implementation 5.6.2 Measurement Results 5.7 Multibit Full Feedforward sigma-delta Modulator Design 5.7.1 Optimized Loop Coefficients 5.7.2 Circuit Implementation 5.8 Conclusion 6 Flash ADC Design in Deep-Submicron CMOS 6.1 Introduction 6.2 Mismatch Study in Deep-Submicron CMOS Technologies 6.2.1 Mismatch of Components

Libin Yao

Papers

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Ieee transactions on circuits and systems—ii: express briefs

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS"