There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Massive multiple-input multiple-output MIMO is one of themost promising technologies for the next generation of wirelesscommunication networks because it has the potential to providegame-changing improvements in spectral efficiency SE and energyefficiency EE. This monograph summarizes many years ofresearch insights in a clear and self-contained way and providesthe reader with the necessary knowledge and mathematical toolsto carry out independent research in this area. Starting froma rigorous definition of Massive MIMO, the monograph coversthe important aspects of channel estimation, SE, EE, hardwareefficiency HE, and various practical deployment considerations.From the beginning, a very general, yet tractable, canonical systemmodel with spatial channel correlation is introduced. This modelis used to realistically assess the SE and EE, and is later extendedto also include the impact of hardware impairments. Owing tothis rigorous modeling approach, a lot of classic "wisdom" aboutMassive MIMO, based on too simplistic system models, is shownto be questionable.

https://www.nowpublishers.com/article/DownloadSummary/SIG-093

Massive MIMO Networks: Spectral, Energy, and Hardware Efficiency

Fast changing, increasingly complex, and diverse computing platforms pose central problems in scientific computing: How to achieve, with reasonable effort, portable optimal performance? We present SPIRAL, which considers this problem for the performance-critical domain of linear digital signal processing (DSP) transforms. For a specified transform, SPIRAL automatically generates high-performance code that is tuned to the given platform. SPIRAL formulates the tuning as an optimization problem and exploits the domain-specific mathematical structure of transform algorithms to implement a feedback-driven optimizer. Similar to a human expert, for a specified transform, SPIRAL "intelligently" generates and explores algorithmic and implementation choices to find the best match to the computer's microarchitecture. The "intelligence" is provided by search and learning techniques that exploit the structure of the algorithm and implementation space to guide the exploration and optimization. SPIRAL generates high-performance code for a broad set of DSP transforms, including the discrete Fourier transform, other trigonometric transforms, filter transforms, and discrete wavelet transforms. Experimental results show that the code generated by SPIRAL competes with, and sometimes outperforms, the best available human tuned transform library code.

/pdf/spiral-code-generation-for-dsp-transforms-4219bd16gh.pdf

SPIRAL: Code Generation for DSP Transforms

There has been a great deal of material in the area of discrete-time transforms that has been published in recent years. This book does an excellent job of presenting important aspects of such material in a clear manner. The book has 11 chapters and a very useful appendix. Seven of these chapters are essentially devoted to the Fourier series/transform, discrete Fourier transform, fast Fourier transform (FFT), and applications of the FFT in the area of spectral estimation. Chapters 8 through 10 deal with many other discrete-time transforms and algorithms to compute them. Of these transforms, the KarhunenLoeve, the discrete cosine, and the Walsh-Hadamard transform are perhaps the most well-known. A lucid discussion of number theoretic transforms i5 presented in Chapter 11. This reviewer feels that the authors have done a fine job of compiling the pertinent material and presenting it in a concise and clear manner. There are a number of problems at the end of each chapter, an appreciable number of which are challenging. The authors have included a comprehensive set of references at the end of the book. In brief, this book is a valuable contribution to the general areas of signal processing and communications. It can be used for a graduate level course in perhaps two ways. One would be to cover the first seven chapters in great detail. The other would be to cover the whole book by focussing on different topics in a selective manner. This book  by  Elliott  and Rao  is extremely  useful to researchers/engineers who are working  in the areas of signal processing and communications. It i s also an excellent reference book, and hence a valuable addition to one’s library

http://ieeexplore.ieee.org/iel5/5/31347/01457444.pdf

Multirate digital signal processing

We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties that simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared with a log-likelihood domain implementation, requires less irregular and smaller memories. This simplification, together with the gains in the metric sorter, lead to $ 56\%$ to $137\%$ higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large block-lengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.

LLR-Based Successive Cancellation List Decoding of Polar Codes

The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

/pdf/pipelined-radix-2-k-feedforward-fft-architectures-5dku5xiwia.pdf

Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

The explosive demand in wireless-capable devices, especially with the proliferation of multiple standards, indicates a great opportunity for adoption of wireless technology at a mass-market level. The communication devices of both today and the future will have not only to allow for a variety of applications, supporting the transfer of characters, audio, graphics, and video data, but they will also have to maintain connection with many other devices rather than with a single base station, in a variety of environments. Moreover, to provide various services from different wireless communication standards with higher capacities and higher data-rates, fully integrated and multifunctional wireless devices will be required. Multifunctional circuits and systems can be made profitable by a large scale of integration, elimination of external components, reduction of silicon area, and extensive reuse of resources. Integration of (Bi)CMOS transceiver RF front-end and analog baseband circuits with computing CMOS circuits on the same silicon chip further reduces costs of multifunctional mobile devices. However, as batteries continue to determine the lifetime and size of mobile equipment, further extension of capabilities of wearable and wireless devices will depend critically on the integrated circuits and systems solutions. The demand for multifunctional and multi-mode wireless-capable devices is accompanied by many significant challenges at system, circuit, and technology levels. In the Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications, we are looking for circuits and systems solutions for multiple communication standards. Examples of topics qualifying for the special issue include: • Adaptive radio circuits and systems • Multifunctional multistandard multi-band circuits and systems • Software-defined radio circuits and systems • Cognitive radio circuits and systems • Low-voltage low-power RF and analog circuits for future generations wireless systems • Ultra Wide Band circuits and systems

Ieee transactions on circuits and systems—ii: express briefs

Lower bounds for problems related to realizing multiplication by constants with shifts, adders, and subtracters are presented. These lower bounds are straightforwardly calculated and have applications in proving the optimality of solutions obtained by heuristics.

Lower Bounds for Constant Multiplication Problems

Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. An adder graph type algorithm for solving the MCM problem is introduced with a novel heuristic inspired by difference methods. It is shown that the results is as good or better as previous state of the art under most conditions. Furthermore, the proposed algorithm does not rely on look-up tables.

A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems

By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits The average savings are more than 25% for 19 bits compared with CSD multipliers The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets Thus, fewer graphs need to be evaluated A classification of the graphs reduces the effort to search the coefficient space further

Oscar Gustafsson

Papers

Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

Ieee transactions on circuits and systems—ii: express briefs

Lower Bounds for Constant Multiplication Problems

A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems

Extended results for minimum-adder constant integer multipliers