This paper demonstrates and compares three configurations for ISFET arrays fabricated in unmodified CMOS that facilitate chemical imaging with linear pH-to-output conversion. Specifically, the typical voltage-mode source-follower configuration is compared against our recently proposed current-mode approach using an ISFET in velocity saturation. These two topologies are also compared against an extension of the current-mode topology to include a programmable-gate capacitor inside the pixel stack for offset compensation. Various performance metrics, such as linearity, speed, power consumption, size, attenuation, and noise have been experimentally measured to quantify the performance of each approach and a figure-of-merit (FoM) has been defined to capture the overall performance. Using this FoM, the current-mode approach results in the best overall performance. Through this paper, however, the relative merits and limitations of each approach are identified to be used as a guide for future designs which are usually application-specific. Furthermore, we illustrate methods used to obtain standard ISFET performance metrics in order to standardize the comparison of ISFET arrays using the figure-of-merit.

ISFET Arrays in CMOS: A Head-to-Head Comparison Between Voltage and Current Mode

In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation, and the full-depletion approximation to obtain the charge transfer current. The proposed physics-based model is fully validated with technology computer-aided design simulations, i.e., stationary and optoelectrical simulations. The development of such a compact model for PPD represents an essential step toward the design, simulation, and optimization of PPD-based pixels in CMOS image sensors.

/pdf/compact-modeling-of-charge-transfer-in-pinned-photodiodes-4qb0vbc4yy.pdf

Compact Modeling of Charge Transfer in Pinned Photodiodes for CMOS Image Sensors

The charge holding capacity of a pinned photodiode (PPD) in CMOS image sensors (CISs) is determined by the capacitance of the photodiode. A PPD with a higher full-well capacity (FWC) is desirable for a higher dynamic range and image contrast thereby improving the image quality. The dependence of FWC of a PPD on light intensity and integration time is reported in the literature. However, there is no generalized method to estimate the PPD capacitance. The reported models assume the PPD capacitance to be constant and independent of operating conditions. This paper presents an improved model to accurately estimate the dynamic behavior of the PPD capacitance at low and high light intensity levels and varying temperature in CISs. It is observed that the logarithmic increase in light intensity and integration time increases the photodiode capacitance linearly. The model shows good agreement with the simulated and measured values of photodiode capacitance.

Dynamic Capacitance Model of a Pinned Photodiode in CMOS Image Sensors

This letter introduces a 5-transistors (5T) implementation of CMOS Image Sensors (CIS) pixels enabling the combination of deep sub-electron noise performance with wide dynamic range (DR). The 5T pixel presents a new technique to reduce the sense node capacitance without any process refinements or voltage level increase and features adjustable conversion gain (CG) to enable wide dynamic imaging. The implementation of the proposed 5T pixel in a standard 180nm CIS process demonstrates the combination of a measured high CG of 250 ${\mu V/e^{-}}$ and low CG of 115 ${\mu V/e^{-}}$ with a saturation level of about 6500 e− offering photo-electron counting capability without compromising the DR and readout speed.

/pdf/a-cmos-image-sensor-pixel-combining-deep-sub-electron-noise-5cz4vjznou.pdf

A CMOS Image Sensor Pixel Combining Deep Sub-Electron Noise With Wide Dynamic Range

This paper presents a highly linear CMOS image sensor (CIS) designed in a commercial 0.18- $\mu$ m CIS technology. A new type of pixel is proposed based on the linearity analysis of a conventional 4T active pixel. The new type of pixel can mitigate the nonlinearity caused by the in-pixel source follower (SF) transistor. In addition, the optimization of the pixel design, a digitally assisted calibration method is proposed to further reduce the nonlinearity of the image sensor, especially, the nonlinearity caused by the integration capacitor ( $C_{\mathrm {FD}}$ ) on the floating diffusion (FD) node. A hybrid behavioral model is proposed to validate the calibration method. Experimental results show that the new type of pixel has a better linearity performance comparing with that of the typical 4T pixel. TCAD simulation results are used to help explain the spillback effect in the transfer transistor’s channel. With the digital calibration, the linearity performances of the pixels in different settings have been improved.

Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

Liqiang Han

Papers

A Charge Transfer Model for CMOS Image Sensors

Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration