An overview is presented of the current state-of-the-art in silicon nanophotonic ring resonators. Basic theory of ring resonators is discussed, and applied to the peculiarities of submicron silicon photonic wire waveguides: the small dimensions and tight bend radii, sensitivity to perturbations and the boundary conditions of the fabrication processes. Theory is compared to quantitative measurements. Finally, several of the more promising applications of silicon ring resonators are discussed: filters and optical delay lines, label-free biosensors, and active rings for efficient modulators and even light sources.

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Silicon microring resonators

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

This Review covers the state-of-the-art technologies on photonics-based terahertz communications, which are compared with competing technologies based on electronics and free-space optical communications. Future prospects and challenges are also discussed. Almost 15 years have passed since the initial demonstrations of terahertz (THz) wireless communications were made using both pulsed and continuous waves. THz technologies are attracting great interest and are expected to meet the ever-increasing demand for high-capacity wireless communications. Here, we review the latest trends in THz communications research, focusing on how photonics technologies have played a key role in the development of first-age THz communication systems. We also provide a comparison with other competitive technologies, such as THz transceivers enabled by electronic devices as well as free-space lightwave communications.

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Advances in terahertz communications accelerated by photonics

The nonlinearities in silicon are diverse. This Review covers the wealth of nonlinear effects in silicon and highlights the important applications and technological solutions in nonlinear silicon photonics. The increasing capability for manufacturing a wide variety of optoelectronic devices from polymer and polymer–silicon hybrids, including transmission fibre, modulators, detectors and light sources, suggests that organic photonics has a promising future in communications and other applications.

Nonlinear silicon photonics

Integrated optical circuits based on silicon-on-insulator technology are likely to become the mainstay of the photonics industry. Over recent years an impressive range of silicon-on-insulator devices has been realized, including waveguides1,2, filters3,4 and photonic-crystal devices5. However, silicon-based all-optical switching is still challenging owing to the slow dynamics of two-photon generated free carriers. Here we show that silicon–organic hybrid integration overcomes such intrinsic limitations by combining the best of two worlds, using mature CMOS processing to fabricate the waveguide, and molecular beam deposition to cover it with organic molecules that efficiently mediate all-optical interaction without introducing significant absorption. We fabricate a 4-mm-long silicon–organic hybrid waveguide with a record nonlinearity coefficient of γ ≈ 1 × 105 W−1 km−1 and perform all-optical demultiplexing of 170.8 Gb s−1 to 42.7 Gb s−1. This is—to the best of our knowledge—the fastest silicon photonic optical signal processing demonstrated. A silicon–organic hybrid slot waveguide with a strong optical nonlinearity is demonstrated to perform ultrafast all-optical demultiplexing of high-bit-rate data streams. The approach could form the basis of compact high-speed optical processing units for future communication networks.

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All-optical high-speed signal processing with silicon–organic hybrid slot waveguides

We present a number of compact wavelength-selective elements implemented in silicon-on-insulator (SOI) photonic wires. These include arrayed waveguide gratings (AWGs), Mach-Zehnder lattice filters (MZLFs), and ring resonators. The circuits were fabricated with deep UV lithography. We also address the sensitivity of photonic wires to phase noise by selectively broadening the waveguides, and demonstrate this in a compact AWG with -20 dB crosstalk and an insertion loss of 2.2 dB for the center channels

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Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS ® process is used, realizing narrow trenches with larger DOF and less LER. Fo r mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is tr ansferred successfully in th e underlying low-k material. Keywords: double patterning, 50nm half pitch, RELACS

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the
possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double
patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in
pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems
conceived for the 65nm node to print 32nm node designs.
In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm
logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have
been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every
design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule
Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process
window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure
tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions
and present a new design rule for double patterning compliance checking applicable to full-chip scale.

Double patterning design split implementation and validation for the 32nm node

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET).
One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition
of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning
requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that
occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an
optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a
1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22
[2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist
features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and
OPC without encountering mask constraints.
Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to
random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of
DP requires the evolution and adoption of design restrictions by specifically tailored design rules.
The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a
production environment. As with any dual-mask RET application, there are the classical overlay requirements between
the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to
maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration.
For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA
industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go
beyond this with the coupling of their model-based and process-window applications.
This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA
immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design
decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA
solutions were further analyzed and quantified utilizing a verification flow.

Double pattern EDA solutions for 32nm HP and beyond

Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k1 imaging factor for each patterning step. With combined patterns, we can achieve overall k1 factor that exceeds the conventional Rayleigh resolution limit. 

This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or one-sixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

Vincent Wiaux

Papers

Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Double patterning design split implementation and validation for the 32nm node

Double pattern EDA solutions for 32nm HP and beyond

Application challenges with double patterning technology (DPT) beyond 45 nm