Patent
Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
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TLDR
In this article, a sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions.Abstract:
A sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions. The source/drain regions are formed by ion implantation using the expendable structure (diamond-like-carbon) as a mask. After the expendable structure has performed its further purpose of protecting the gate dielectric from contamination during the annealing cycle, the structure is easily removed by O 2 plasma and replaced by a conventional metal gate material.read more
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Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
Veena Misra,Suresh Venkatesan,Christopher C. Hobbs,B. Smith,Jeffrey S. Cope,Earnest B. Wilson +5 more
Abstract: A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
Patent
Method of forming dual metal gate structures for CMOS devices
Scott R Summerfelt,Glen D. Wilks +1 more
TL;DR: In this article, the instant invention is a method of creating a first transistor having a first gate electrode and a second transistor with a second gate electrode on a semiconductor substrate, the method comprising the steps of:
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High-performance cmos soi device on hybrid crystal-oriented substrates
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TL;DR: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device was created upon a second different surface that was optimal for the other device as mentioned in this paper.
References
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Journal ArticleDOI
Reactive ion etching of diamond
G. S. Sandhu,Wei-Kan Chu +1 more
TL;DR: In this article, the authors used reactive ion etching with O2 and H2 to remove surface layers of diamond, achieving a rate of 560 A/min for thin carbon films and 350 A/m for natural type II-A diamonds using 300 eV oxygen ions.
Patent
Method of manufacturing a field effect transistor device having a multilayer gate electrode
TL;DR: In this paper, the Schottky barrier gate field effect transistor (SGFE transistor) was proposed, where the gate electrode is fixed to an insulative portion formed on the channel region.
Patent
Method for making a w/tin contact
TL;DR: In this article, a spin-on glass is used as an etch mask to remove the portion of titanium nitride which is located outside the opening, which is then used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening.
Patent
Submicron patterning without using submicron lithographic technique
TL;DR: In this article, vertical "zero undercut" etching techniques are employed to convert the sub-micron thickness of a deposited thin film conductor layer and a thin film insulation layer into submicron gate widths that can be used in a wide variety of devices, including MOS field effect devices.
Journal ArticleDOI
p-channel germanium MOSFETs with high channel mobility
TL;DR: In this article, the fabrication and performance of p-channel germanium MOSFETs having a nitrided native oxide gate insulator are reported and a self-aligned dummy-gate process suitable for circuit integration is utilized.