Showing papers by "Luca Sterpone published in 2010"

Microvesicles Derived from Adult Human Bone Marrow and Tissue Specific Mesenchymal Stem Cells Shuttle Selected Pattern of miRNAs

Abstract: Background: Cell-derived microvesicles (MVs) have been described as a new mechanism of cell-to-cell communication. MVs after internalization within target cells may deliver genetic information. Human bone marrow derived mesenchymal stem cells (MSCs) and liver resident stem cells (HLSCs) were shown to release MVs shuttling functional mRNAs. The aim of the present study was to evaluate whether MVs derived from MSCs and HLSCs contained selected micro-RNAs (miRNAs). Methodology/Principal Findings: MVs were isolated from MSCs and HLSCs. The presence in MVs of selected ribonucleoproteins involved in the traffic and stabilization of RNA was evaluated. We observed that MVs contained TIA, TIAR and HuR multifunctional proteins expressed in nuclei and stress granules, Stau1 and 2 implicated in the transport and stability of mRNA and Ago2 involved in miRNA transport and processing. RNA extracted from MVs and cells of origin was profiled for 365 known human mature miRNAs by real time PCR. Hierarchical clustering and similarity analysis of miRNAs showed 41 co-expressed miRNAs in MVs and cells. Some miRNAs were accumulated within MVs and absent in the cells after MV release; others were retained within the cells and not secreted in MVs. Gene ontology analysis of predicted and validated targets showed that the high expressed miRNAs in cells and MVs could be involved in multi-organ development, cell survival and differentiation. Few selected miRNAs shuttled by MVs were also associated with the immune system regulation. The highly expressed miRNAs in MVs were transferred to target cells after MV incorporation. Conclusions: This study demonstrated that MVs contained ribonucleoproteins involved in the intracellular traffic of RNA and selected pattern of miRNAs, suggesting a dynamic regulation of RNA compartmentalization in MVs. The observation that MV-highly expressed miRNAs were transferred to target cells, rises the possibility that the biological effect of stem cells may, at least in part, depend on MV-shuttled miRNAs. Data generated from this study, stimulate further functional investigations on the predicted target genes and pathways involved in the biological effect of human adult stem cells.

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Abstract: Introduction- Re-configurable Field Programmable Gate Arrays: basic concepts- Re-configurable Field Programmable Gate Arrays: failure modes and analysis- Re-configurable Field Programmable Gate Arrays: hardening solutions- Commercial off the shelf FPGAs- Radiation hardened SRAM-based FPGAs- Conclusion

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs

Abstract: Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Simultaneously the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from signal processing to networking. SRAM-based FPGAs are the candidate devices to achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA’s functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29p on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA’s configuration memory. Accurate analyses of SEUs sensitivity and performance optimization have been performed on a real microprocessor core demonstrating an improvement of performances of more than 62p.

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

Abstract: This paper presents an enhanced design flow for the implementation of hardened systems on SRAM-based FPGAs, able to cope with the occurrence of Single Event Upsets (SEUs). The framework integrates three strategies independently designed to tackle the problem of SEUs; first a systematic methodology is used to harden the circuit exploiting an enhanced TMR-based technique, coupled with partial dynamic reconfiguration. Then, a robustness analysis is performed to identify possible TMR failures, eventually solved by a specific local re-design of the critical portions of the implementation. We present the overall flow and the benefits of the solution, experimentally evaluated on a realistic circuit.

On the mitigation of SET broadening effects in integrated circuits

Abstract: Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event Transient (SET) pulses that may be generated and propagated through the combinational logic, leading to misbehaviors. SETs are mainly generated by high-energy particles that strikes the circtuit near a junction, resulting in a significant charge injection/depletion process, that may produce spurious pulses. These can propagate and change their shape traversing the combinational logic paths, sometimes being broadened and amplified sometimes being filtered. In this paper, we present a place and route algorithm for integrated circuit design, which is able to mitigate and filter the erroneous effects of SETs. The proposed solution has been experimentally evaluated by means of electrical pulse injection within logic resources of several benchmark Integrated Circuits (ICs) implemented in a Flash-based FPGA and by accurate timing analyses. Preliminary results confirm the mitigation of SET broadening effects by acting on physical place and route constraints. On the selected benchmark circuit the algorithm decreases the SET sensitiveness more than 70% with respect to not hardened circuits. Besides, the solution does not introduce any area overhead or delay penalties.

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs

Abstract: Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new FPGA devices very advantageous for space and avionics computing. However, larger levels of integration makes FPGA?'s configuration memory more prone to suffer Multi-Cell Upset errors (MCUs), caused by a single radiation particle that can flip the content of multiple nearby cells. In particular, MCUs are on the rise for the new generation of SRAM-based FPGAs, since their configuration memory is based on volatile programming cells designed with smaller geometries that result more sensitive to proton- and heavy ion-induced effects. MCUs drastically limits the capabilities of specific hardening techniques adopted in space-based electronic systems, mainly based on Triple Modular Redundancy (TMR). In this paper we describe a new placement algorithm for hardening TMR circuits mapped on SRAM-based FPGAs against the effects of MCUs. The algorithm is based on layout information of the FPGA?'s configuration memory and on metrics related to the logic and interconnection resources locations. Experimental results obtained from MCU static analysis on a set of benchmark circuits hardened by the proposed algorithm prove the efficiency of our approach.

A novel scalable and reconfigurable emulation platform for embedded systems verification

Abstract: Modern embedded systems are characterized by a heterogeneous architecture including several modules (e.g., DSPs, memories and mixed-signal IPs) often integrated with one or more microprocessor cores controlling the system functionalities by means of embedded software programs. The verification of such a kind of systems has become a challenge due to their increasing complexity that makes traditional simulation and emulation techniques unaffordable methods for current quality and time-to-market constraints. This paper presents a new platform for the hardware and software verification of modern embedded systems based on a reconfigurable device. The main novelty consists in an infrastructure architecture containing a signal processing IP and a microprocessor core flexibly interfaced with the device under validation, aimed at the overall reduction of the design verification time. It also provides a dynamic interface supporting the software verification of the embedded system microprocessors. The proposed environment is fully scalable and adaptable to the requirements of a general purpose embedded system, enabling advanced verification flows at different phases of design and integration without time expensive interface modification. Experimental and performance analysis on a real industrial case study are reported proving the effectiveness of the proposed solution.

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

Abstract: The higher resiliency of Flash-based FPGAs to Single Event Upsets (SEUs) with respect to other non radiation-hardened devices, such as SRAM-based FPGAs, are increasing more and more their demand for avionic and space applications, where a harsh environment rich in ionizing radiation has to be faced. In this type of devices other transient faults tend to dominate over SEUs, especially when the device operates at high frequency. In this scenario, it is expected that Single Event Transient (SET) faults will predominate. As a result, designers will still need prediction techniques to forecast the effects of ionizing radiation in their designs. Although radiation testing is a feasible method for evaluating circuit sensitiveness against SETs, it is hard to implement, very expensive, and it can be used only in later phases of the design process, when a prototype of the system is available. On the other hand, simulation techniques need a first technology characterization step and also require a very detailed model for being effective; moreover they are application dependent. In this paper we propose a new software tool for analyzing designs implemented in Flash-based FPGAs and estimating SET sensitiveness. The evaluation process is static, as it does not entail any simulation. In particular, it provides worst-case results, thus being intrinsically more conservative than other dynamic methods. Experimental results are presented comparing the ones coming from radiation testing and the results provided by the presented tool. They validate the proposed approach.

A New Soft-Error Resilient Voltage-Mode Quaternary Latch

Abstract: Multiple-valued logic circuits represent nowadays a new technology challenge to realize integrated circuits using less silicon area and having low power and high frequencies characteristics. Above this technology, quaternary logic is increasingly attractive for Field Programmable Gate array devices, where the costs of area, power and interconnections delay play a key role in the overall circuit costs. These characteristics make quaternary logic circuits appealing for space applications where area and power reduction are extremely desired. In order to enable multiple-value logic for space applications it is necessary to evaluate and harden this technology against radiation effects inducing soft-errors. In this paper, we firstly propose a characterization of a voltage-mode quaternary latch in the presence of induced transients that vary in intensity, local and time of transient injection as well as the value of the input stimulus. Secondly, we present a new architecture of the latch circuit in order to allow the detection and correction of any radiation-induced effect. Detailed experimental analysis demonstrated the radiation sensitivity to transient effects of classical and hardened quaternary logic latch. Results demonstrated that the proposed design results fully robust to soft error with respect to the standard design.