Lucas L. Sanches

TL;DR: The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.

TL;DR: This paper discusses tradeoffs that can influence both the effective acceleration factor (“speed”) and power requirements of such on-chip learning accelerators, and addresses how the circuit requirements are somewhat reminiscent of, yet significantly different from, the well-known requirements found in conventional memory applications.

TL;DR: Large arrays of the same nonvolatile memories being developed for Storage-Class Memory (SCM) - such as Phase Change Memory and Resistance RAM - can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as synaptic “weight.”

TL;DR: This work analyzes neuron circuit needs for implementing back-propagation in NVM arrays and introduces approximations to reduce design complexity and area and shows that by leveraging the resilience of the algorithm to error, it can use practical circuit approaches yet maintain competitive test accuracies on ML benchmarks.

TL;DR: Large arrays of the same nonvolatile memories being developed for storage-class memory (SCM) – such as phase-change memory (PCM) and resistive RAM) – can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as synaptic “weight.”