Alessandro Fumarola

TL;DR: The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.

TL;DR: This paper discusses tradeoffs that can influence both the effective acceleration factor (“speed”) and power requirements of such on-chip learning accelerators, and addresses how the circuit requirements are somewhat reminiscent of, yet significantly different from, the well-known requirements found in conventional memory applications.

TL;DR: Improvements to non-filamentary RRAM devices based on Pr0.7Ca0.3MnO3 by introducing an MoOx buffer layer together with a reactive Al electrode, and on device measurements designed to help gauge the performance of these devices as bidirectional analog synapses for on-chip acceleration of the backpropagation algorithm.

TL;DR: The “jump-table” concept is discussed, previously introduced to model real-world NVM such as PCM or PCMO, to describe the full cumulative distribution function (CDF) of conductance-change at each device conductance value, for both potentiation (SET) and depression (RESET).

TL;DR: Large arrays of the same nonvolatile memories being developed for Storage-Class Memory (SCM) - such as Phase Change Memory and Resistance RAM - can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as synaptic “weight.”