M. Mendell

TL;DR: An overview of the BlueGene/L Supercomputer, a massively parallel system of 65,536 nodes based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second).

TL;DR: SPL abstracts away the complexity of the distributed system, instead exposing a simple graph-of-operators view to the user and provides a strong type system and user-defined operator models.

TL;DR: Preliminary results indicate that the high-performance networks on BG/L will allow us to use FFT-based techniques for periodic electrostatics with reasonable speedups on 512-1024 node count partitions even for systems with as few as 5000 atoms.

TL;DR: The system software stack for BG/L creates a programming and operating environment that harnesses the raw power of this architecture with great effectiveness and specialized the services provided by each component of the system architecture to deliver high performance to applications.

TL;DR: The design of a dual-issue single-instruction, multiple-data-like (SIMD-like) extension of the IBM PowerPC® 440 floating-point unit (FPU) core and the compiler and algorithmic techniques to exploit it are described and measurements show that the combination of algorithm, compiler, and hardware delivers a significant fraction of peak floating- point performance for compute-bound-kernels, such as matrix multiplication.