The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

Passivation issues in active pixel CMOS image sensors

Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.

Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. The use of analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (Vdd) nor the gate length (Lg) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (Lg) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. The suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area

Power Optimization for SRAM and Its Scaling

Analog device design in the deep sub-micron regime is particularly challenging due to conflicting device performance requirements and the circuit requirements in analog applications. It is shown that novel single pocket devices improve the intrinsic analog performance compared to the conventional super steep retrograde devices, within the constraints imposed by circuit requirements. The effect of gate oxide thickness variation on the analog performance of the novel single pocket and conventional super steep retrograde n-channel MOSFETs is also evaluated. It is shown that for constraints on power supply scaling, single pocket structures offer a better option for low-power analog applications.

Analog device design for low power mixed mode applications in deep submicron CMOS technology

In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.

High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

In this paper, we focus on hydrogen related processes and its impact on system LSI. Hydrogen affects not only DRAM performance but also reliability characteristics for MOSFET such as NBTI (negative bias temperature instability), HCI (hot carrier injection), and TDDB. We demonstrate that NBTI and HCI are degraded by excess hydrogen while improving retention characteristics of eDRAM. It is shown for the first time that anomalous degradation in TDDB for downsized MOSFET is caused by the compressive stress by STI and shows strong correlation to hydrogen processes. The optimization of hydrogen processes is indispensable for highly reliable system LSI in future generations.

http://www.vlsisymposium.org/Past/02web/technology/tec_pdf/T22p2.pdf

New guideline for hydrogen treatment in advanced system LSI

The hot-carrier (HC) instability for surface channel PMOSFETs is investigated intensively We found from experimental data that hot-carrier injection occurs at the channel center under the most serious stress condition of V/sub gs/=V/sub ds/ and that a physical mechanism similar to NBTI is responsible for degradation at room temperature, and confirmed from hydrodynamic simulations We demonstrate that mechanical stress resulting from the sidewall spacer accelerates this anomalous degradation in short-channel PMOS under hot-carrier stress We show that management of this degradation mechanism is indispensable for achieving high reliability in future generation PMOS devices

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond

In this paper, mixed signal LSI operating at a single drain voltage of 15 V is shown Integration of high performance logic MOSFET with analog MOSFET is achieved by optimizing channel structures Very high performance and competitive drive currents of 830 /spl mu/A//spl mu/m for nMOS and 390 /spl mu/A//spl mu/m for pMOS at 1 nA//spl mu/m off currents are achieved by careful halo optimization in logic MOSFET In analog part, indium channel is applied for satisfying low threshold voltage specification which comes from dynamic range viewpoint This indium channel MOSFET shows superior analog performance By applying indium retrograde channel, high DC gain values which are approximately ten times lager than the uniform boron channel case are achieved in addition to wide bandwidth and good Vth matching It is found that well anneal temperature which is carried out soon after channel ion implantation is very sensitive to analog performance in indium retrograde channel This optimization is significant for DC gain and matching

M. Nishigori

Papers

High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

New guideline for hydrogen treatment in advanced system LSI

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond

A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node