A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.

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Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

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Noise modeling for RF CMOS circuit simulation

In this paper a review of the more "fundamental" concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.

Scaling the gate dielectric: materials, integration, and reliability

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

NiSi salicide technology for scaled CMOS

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

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Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

Future perspective and scaling down roadmap for RF CMOS

Results of the high-frequency AC characteristics of 1.5 nm direct-tunneling gate oxide MOSFET's were shown for the first time. Very high cutoff frequencies of more than 150 GHz were obtained at gate lengths of sub-0.1 /spl mu/m regime due to the high transconductance. Excellent NF/sub min/ value of 0.51 dB was obtained at high-frequency operation of 2 GHz. Also, good operation of the 1.5 nm gate oxide CMOS ring oscillator has been confirmed.

High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.

Eiji Morifuji

Papers

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

Future perspective and scaling down roadmap for RF CMOS

High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

Future perspective and scaling down roadmap for RF CMOS