K. Miyamoto

TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.

TL;DR: In this article, the authors focus on hydrogen related processes and its impact on system LSI and demonstrate that NBTI and HCI are degraded by excess hydrogen while improving retention characteristics of eDRAM.

TL;DR: The hot-carrier instability for surface channel PMOSFETs is investigated intensively in this article, where the authors found that the hotcarrier injection occurs at the channel center under the most serious stress condition of V/sub gs/=V/sub ds/ and that a physical mechanism similar to NBTI is responsible for degradation at room temperature, and confirmed from hydrodynamic simulations.

TL;DR: In this paper, a mixed signal LSI operating at a single drain voltage of 15 V is shown, and the integration of high performance logic MOSFET with analog MOS-FET is achieved by optimizing channel structures.

TL;DR: Novel circuit design and process technologies for leading-edge products using extremely regular layout methodology and SiP (System in Package) with CoC (chip on chip) for 40nm technology node products are reported.