Proceedings ArticleDOI
A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node
Eiji Morifuji,A. Oishi,Katsura Miyashita,S. Aota,M. Nishigori,H. Ootani,T. Nakayama,K. Miyamoto,Fumiyoshi Matsuoka,T. Noguchi,Masakazu Kakumu +10 more
- pp 459-462
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In this paper, a mixed signal LSI operating at a single drain voltage of 15 V is shown, and the integration of high performance logic MOSFET with analog MOS-FET is achieved by optimizing channel structures.Abstract:
In this paper, mixed signal LSI operating at a single drain voltage of 15 V is shown Integration of high performance logic MOSFET with analog MOSFET is achieved by optimizing channel structures Very high performance and competitive drive currents of 830 /spl mu/A//spl mu/m for nMOS and 390 /spl mu/A//spl mu/m for pMOS at 1 nA//spl mu/m off currents are achieved by careful halo optimization in logic MOSFET In analog part, indium channel is applied for satisfying low threshold voltage specification which comes from dynamic range viewpoint This indium channel MOSFET shows superior analog performance By applying indium retrograde channel, high DC gain values which are approximately ten times lager than the uniform boron channel case are achieved in addition to wide bandwidth and good Vth matching It is found that well anneal temperature which is carried out soon after channel ion implantation is very sensitive to analog performance in indium retrograde channel This optimization is significant for DC gain and matchingread more
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Journal ArticleDOI
Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications
TL;DR: It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.
Journal ArticleDOI
Analog device design for low power mixed mode applications in deep submicron CMOS technology
TL;DR: In this paper, the effect of gate oxide thickness variation on the analog performance of the single pocket and conventional super steep retrograde n-channel MOSFETs is evaluated.
Proceedings ArticleDOI
Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology
Amitava Chatterjee,Dan M. Mosher,Seetharaman Sridhar,Youngmin Kim,Mahalingam Nandakumar,S. Aur,Zaichen Chen,P. Madhani,Shaoping Tang,R. Aggarwal,S. Ashburn,Hisashi Shichijo +11 more
TL;DR: In this paper, the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits is discussed in this context.
Journal ArticleDOI
Halo and LDD Engineering for Multiple ${\rm V}_{\rm TH}$ High Performance Analog CMOS Devices
TL;DR: In this article, a 0.13mum logic-based mixed-signal CMOS process on a single chip was used for high performance analog (HPA) devices with multiple threshold voltages.
Proceedings ArticleDOI
Channel Engineering Study for 50 nm P-Channel MOSFET
TL;DR: In this article, an extensive comparison of 50 nm pMOSFETs processed with either conventional or with retrograde channel profiles is presented, and the impacts of annealing conditions (RTA or spike ) are investigated.
References
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Journal ArticleDOI
CMOS technology for mixed signal ICs
Marcel Pelgrom,Maarten Vertregt +1 more
TL;DR: The consequences of the present developments on mixed-signal ICs are discussed briefly in this paper, where the development of some analogue parameters as a function of process generation is analysed.
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