Makoto Ishikawa

TL;DR: A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process and provides a resume-standby mode with a quick recovery feature using data retention of memory.

TL;DR: In this article, an embedded processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS.

TL;DR: An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS, suitable for digital consumer appliances.

TL;DR: A heterogeneous multi-core SoC for applications, such as digital TV systems with IP networks (IP-TV) including image recognition and database search, and automatic parallelization compilers analyze parallelism of the data flow, generate coarse grain tasks, and schedule tasks to minimize execution time considering data transfer overhead for general-purpose CPU and FE.

TL;DR: In this article, a microcontroller with a floating-point arithmetic logic unit is presented, in which the increase in the program code for performing floating point arithmetic is suppressed, and the processing overhead for converting fixed-point data into floating point data is reduced.