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Design Of Analog Cmos Integrated Circuits

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Design Of Integrated Circuits For Optical Communications

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630\ \mu\text{m}\! \times\! 570\ \mu\text{m}^{2}$ .

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

This paper presents an ultra-low-voltage and power-efficient 10 bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC). For reducing the digital-to-analog converter (DAC) capacitance and comparator requirement, we propose a hybrid architecture comprising a coarse 7 bit SAR ADC and fine 3.5 bit time-to-digital converter (TDC). The Vcm-based switching method is adopted for coarse conversion to reduce DAC power and maintain common mode. The residual voltage after coarse conversion is converted to time domain, and the fine TDC detects the least three bits with 0.5 bit redundancy by using a Vernier delay structure. Offset calibration and delay time locking are implemented to guarantee the ADC performance under process variation. The test chip, fabricated in 90 nm CMOS technology, occupied a core area of ${0.04}\;{{\text{m}}{\text{m}}^{2}}$ . With a 0.4 V supply and a Nyquist rate input, the prototype consumed 200 nW at 250 kS/s and achieved an ENOB of 8.63 bits and a SFDR of 78.5 dB. The operation frequency was scalable from 250 kS/s to 4 MS/s. The converter had a power supply range of 0.4–0.7 V, and the figure of merit (FoM) were 2.02–5.16 fJ/conversion step.

A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS

An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm 2 .

A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS

This paper addresses the issue of deceptive jamming against synthetic aperture radar (SAR) by using 1-bit sampling and time-varying threshold (TVT). With 1-bit intercepted SAR signal, the multipliers involved in a convolution is replaced by xnor gates, which considerably simplify the jamming signal generation. Moreover, the TVT is used for 1-bit quantization before retransmission to retain the relative amplitude information of the jamming signal. As a result, the proposed deceptive jamming schemes are superior to their conventional counterpart in terms of realization. Effects of harmonics and oversampling are analyzed to evaluate the performance degradations caused by the 1-bit sampling and TVT. Simulation results are provided to confirm the validity of the proposed schemes.

Deceptive SAR Jamming Based on 1-bit Sampling and Time-Varying Thresholds

An adjustable-gain transimpedance amplifier with a wide linear dynamic range, low power consumption, and low input impedance was designed for a pulsed linear laser detection and ranging system. To extend the linear dynamic range within a low power consumption, some specific techniques are presented. A low-power current-mirror amplifier with a level shifter was used to decrease the input impedance and keep it stable. Adjustable transimpedance gain extends the input dynamic range, and a high-pass filter eliminates the influence of dc operating point drift caused by the variable gain. When implemented in 0.18- ${\mu }\text{m}$ standard CMOS technology, the receiver achieved a high gain of 106 dB with four configurable gain modes, a wide linear output swing of 1 V, an input-referred noise current of $1.52~ {\rm p{A}/ \sqrt {Hz}}$ , and a minimum detectable signal of 400 nA at SNR = 5, leading to a linear dynamic range of 77 dB, and the power consumption in the highest gain mode was 8 mW with a 3.3-V supply.

A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR

This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18- $\mu \text{m}$ CMOS. Non-ideal factors from practical circuit implementations are theoretically considered and modeled in Simulink. To improve the linearity and the reliability of the bootstrapped switch circuit, the body-effect compensation is adopted. The asynchronous clock generation circuit with a variable-time control cell is presented, which optimizes the DAC settling time of the MSB DAC and LSB DAC in an SAR conversion. Verilog codes and a standard digital library make it possible to synthesize the most parts of the VCO-based Nyquist ADC, greatly reducing the design costs. At Nyquist input frequency and a 5 MS/s sampling rate, a signal-to-noise and distortion ratio of 56.7 dB and a spurious-free dynamic range of 72.2 dB are achieved, respectively. The core occupies $450\,\, {\mu }{ \text{m}} {\times } {280}\,\, {\mu }\text{m}$ .

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\mu$ m CMOS

An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

Maliang Liu

Papers

A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS

Deceptive SAR Jamming Based on 1-bit Sampling and Time-Varying Thresholds

A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\mu$ m CMOS

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR