The authors present a sub-Nyquist analog-to-digital converter of wideband inputs. The circuit realises the recently proposed modulated wideband converter, which is a flexible platform for sampling signals according to their actual bandwidth occupation. The theoretical work enables, for example, a sub-Nyquist wideband communication receiver, which has no prior information on the transmitter carrier positions. The present design supports input signals with 2 GHz Nyquist rate and 120 MHz spectrum occupancy, with arbitrary transmission frequencies. The sampling rate is as low as 280 MHz. To the best of the authors' knowledge, this is the first reported hardware that performs sub-Nyquist sampling and reconstruction of wideband signals. The authors describe the various circuit design considerations, with an emphasis on the non-ordinary challenges the converter introduces: mixing a signal with a multiple set of sinusoids, rather than a single local oscillator, and generation of highly transient periodic waveforms, with transient intervals on the order of the Nyquist rate. Hardware experiments validate the design and demonstrate sub-Nyquist sampling and signal reconstruction.

Xampling: Analog to digital at sub-Nyquist rates

We show that the MEMS gyroscopes found on modern smart phones are sufficiently sensitive to measure acoustic signals in the vicinity of the phone. The resulting signals contain only very low-frequency information (<200Hz). Nevertheless we show, using signal processing and machine learning, that this information is sufficient to identify speaker information and even parse speech. Since iOS and Android require no special permissions to access the gyro, our results show that apps and active web content that cannot access the microphone can nevertheless eavesdrop on speech in the vicinity of the phone.

/pdf/gyrophone-recognizing-speech-from-gyroscope-signals-514nfsug55.pdf

Gyrophone: recognizing speech from gyroscope signals

Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce their metastability error rate while increasing the input capacitance. This paper quantifies the benefits and derives an upper bound on the performance by considering kT/C noise and slewing requirements of the circuit driving the system. A frequency-domain analysis of interleaved converters is also presented that sheds light on the corruption mechanisms due to interchannel mismatches. A background timing mismatch calibration technique is proposed and experimentally shown to reduce the image to -75 dB for input frequencies exceeding 500 MHz.

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Design Considerations for Interleaved ADCs

This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

We consider minimal-rate sampling schemes for infinite streams of delayed and weighted versions of a known pulse shape. The minimal sampling rate for these parametric signals is referred to as the rate of innovation and is equal to the number of degrees of freedom per unit time. Although sampling of infinite pulse streams was treated in previous works, either the rate of innovation was not achieved, or the pulse shape was limited to Diracs. In this paper we propose a multichannel architecture for sampling pulse streams with arbitrary shape, operating at the rate of innovation. Our approach is based on modulating the input signal with a set of properly chosen waveforms, followed by a bank of integrators. This architecture is motivated by recent work on sub-Nyquist sampling of multiband signals. We show that the pulse stream can be recovered from the proposed minimal-rate samples using standard tools taken from spectral estimation in a stable way even at high rates of innovation. In addition, we address practical implementation issues, such as reduction of hardware complexity and immunity to failure in the sampling channels. The resulting scheme is flexible and exhibits better noise robustness than previous approaches.

/pdf/multichannel-sampling-of-pulse-streams-at-the-rate-of-cc5enlznam.pdf

Multichannel Sampling of Pulse Streams at the Rate of Innovation

Time-interleaved analog-to-digital converters (TIADCs) are sensitive to various mismatches that distort the sampled signal. Standard TIADC analysis assumes a narrowband sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived and are validated through simulations. In one of the examples presented, it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three.

General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses these issues.

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10
 -9
, and has a power consumption of 1.15 W for the core ADC.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81 mW from a 1.1-V supply.

Manar El-Chammas

Papers

A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration