Journal ArticleDOI
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC
Manar El-Chammas,Xiaopeng Li,Shigenobu Kimura,Kenneth G. Maclean,Jake Hu,Mark Weaver,Matthew Gindlesperger,Scott Kaylor,Robert Floyd Payne,Charles Sestok,William J. Bright +10 more
TLDR
This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process that achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W.Abstract:
This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10
-9
, and has a power consumption of 1.15 W for the core ADC.read more
Citations
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Journal ArticleDOI
Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction
TL;DR: A novel adaptive architecture for blind identification and compensation of frequency response mismatches in 4-channel time-interleaved analog-to-digital-converters (TI-ADCs) using complex second-order statistics based methods is proposed.
Journal ArticleDOI
All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC
TL;DR: The proposed digital adaptive blind background calibration technique for the gain, timing skew, and offset mismatch errors in a time-interleaved analog-to-digital converter (TI-ADC) is applicable to any TI-ADCs with no limitations to the channel number, sub- ADC sampling rate, signal type, and so on.
Journal ArticleDOI
Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs
TL;DR: A method for joint calibration of several types of linear and nonlinear mismatch errors in two-channel TI-ADCs using a normalized least-mean square (N-LMS) algorithm as well as a certain low degree of oversampling for the overall converter to estimate and compensate for the mixed mismatch errors.
Proceedings ArticleDOI
15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC
Manar El-Chammas,Xiaopeng Li,Shigenobu Kimura,Jesse Coulon,Jake Hu,David Smith,Paul E. Landman,Mark Weaver +7 more
TL;DR: The authors present a single-channel 14b 500MS/s switched-current pipelined ADC that does not require background calibration, targeted for wireless infrastructure, and introduces several circuit techniques that reduce the T&H distortion, extend the available amplifier settling time, and enhance the ADC linearity at smaller signal amplitudes.
Journal ArticleDOI
A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs
TL;DR: Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits with inherent defects such as offset, gain, timing-skew misma...
References
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A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
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TL;DR: In this article, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area.
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A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
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Design techniques for high-speed, high-resolution comparators
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
Journal ArticleDOI
Explicit analysis of channel mismatch effects in time-interleaved ADC systems
TL;DR: This paper derives explicit formulas for the mismatch effects when all of offset, gain and timing mismatches exist together in the time-interleaved ADC system and discusses the bandwidth mismatch effect.