M
Manar El-Chammas
Researcher at Texas Instruments
Publications - 21
Citations - 574
Manar El-Chammas is an academic researcher from Texas Instruments. The author has contributed to research in topics: Skew & Comparator. The author has an hindex of 9, co-authored 20 publications receiving 508 citations. Previous affiliations of Manar El-Chammas include Stanford University.
Papers
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Journal ArticleDOI
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
Manar El-Chammas,Boris Murmann +1 more
TL;DR: A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS to improve dynamic performance, and comparator offset calibration to reduce power dissipation.
Journal ArticleDOI
General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs
Manar El-Chammas,Boris Murmann +1 more
TL;DR: Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived, and are validated through simulations, and it is shown that standard analysis can overconstrain the bound on acceptable phaseskew variance by a factor of three.
Proceedings ArticleDOI
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC
Robert Floyd Payne,Charles Sestok,William J. Bright,Manar El-Chammas,Marco Corsi,David Smith,Noam Tal +6 more
TL;DR: A two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency.
Journal ArticleDOI
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC
Manar El-Chammas,Xiaopeng Li,Shigenobu Kimura,Kenneth G. Maclean,Jake Hu,Mark Weaver,Matthew Gindlesperger,Scott Kaylor,Robert Floyd Payne,Charles Sestok,William J. Bright +10 more
TL;DR: This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process that achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W.
Proceedings ArticleDOI
A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration
Manar El-Chammas,Boris Murmann +1 more
TL;DR: In this paper, a 12GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS, which utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation.