Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

/pdf/wireless-implantable-microsystems-high-density-electronic-2s60s28lz9.pdf

Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

This paper describes a technique which uses the differential non linearity (DNL) test data for fault location and identification of the analog components of a flash ADC. In a flash ADC, a fault in the analog subcircuit is uniquely reflected in the transfer function and therefore also in DNL data. This property is exploited to locate a fault and to identify the error value in analog components of the flash ADC. The technique proposed here relies only on DNL test data. Thus the diagnosis can be carried out using at-operating-speed test data. The paper presents relationship between each fault case and its respective DNL pattern. Fault simulation results of a small flash ADC are presented. >

Fault diagnosis of flash ADC using DNL test

An approach to the crosstalk analysis of high-speed interconnects has been developed. The method yields closed-form expressions of the voltage and current transfer functions and time-domain signal waveforms. The results facilitate analytical evaluation of coupling noise, waveform distortion, and propagation delay due to crosstalk inherent in multiconductor interconnects. The method is applicable to the general problem of N coupled lossy and/or dispersive interconnects with arbitrary linear source/load impedances. >

http://ieeexplore.ieee.org/iel2/140/3519/00124711.pdf

Crosstalk analysis of high-speed interconnects and packages

This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure.

/pdf/a-statistical-approach-to-the-estimation-of-delay-dependent-zi68mo9ypi.pdf

A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits

This paper presents a digital scheme to correct undesired skews between couples of clocks of synchronous systems. Correction is automatically and very fastly performed during system run-time. The proposed scheme is self-checking with respect to a wide set of possible internal (permanent as well as temporary) faults, and is easily scalable to account for different skew tolerance/sensitivity requirements. It is suitable to be implemented in VLSI, very deep submicron technology, as well as using field programmable gate arrays.

Self-checking scheme for very fast clocks' skew correction

On-chip calibration technique for delay line based time-to-digital converters (TDC) used in jitter measurement built-in self-test (BIST). The proposed technique utilizes pulse width modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier delay line (VDL) BIST provided a cycle-to-cycle jitter resolution of /spl sim/5 ps. The calibration design consists of digital CMOS components and has a potential die area of 0.03/spl mu/m/sup 2/. Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.

Mani Soma

Papers

Fault diagnosis of flash ADC using DNL test

Crosstalk analysis of high-speed interconnects and packages

A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits

Self-checking scheme for very fast clocks' skew correction

On-chip calibration technique for delay line based BIST jitter measurement