Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

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Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

The test quality of DC parametric manufacturing test sets is evaluated versus the open fault model for analog amplifiers. Using two case studies in CMOS and bipolar technologies, the fault coverage of the test set is shown to be rather low (less than 80%). Several open faults in the signal path remain undetected. When the amplifiers are embedded in a larger circuit, the functional test set is usually unable to detect these faults as well. Detection is strongly correlated to circuit topology in two signal processing circuits used as examples. Test selection guidelines are presented

Fault coverage of DC parametric tests for embedded analog amplifiers

To reduce the test costs of phase noise measurements, we use all-digital methods to detect sinusoidal phase noise components while reducing the need for computation intensive FFT.

A digital method for phase noise measurement

A different approach to reconfigurable systolic arrays is described. In addition to making the interconnection network reconfigurable (to match the topology of the Algorithm flow graph), the authors make the individual processing elements themselves configurable, in order to provide the best match to the computational requirements of individual nodes. Rather than having a fixed instruction set, they hope to tailor the architecture of the different processing elements in such a way as to carry out their functions without the use of instruction streams. This reduces the problems of control and coordination and provides a closer match to the algorithm being implemented. The prototype architecture being developed and an analysis of its application to a particular class of problems (numeric sorting) are described. >

A reconfigurable approach to a systolic sorting architecture

This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new jitter tolerance model is verified with experimental data on cables of various lengths, using both PRBS and T11 test patterns.

Effects of deterministic jitter in a cable on jitter tolerance measurements

This paper presents the structure of a current-based analog scan cell for analog and mixed-signal design-for-test. The cell uses current to represent the analog signal to be scanned and functions identically to a digital scan latch, except of course the scanned signal retains analog information. The concepts of scanning are explained using this structure, and some limitations, under experimental study at this time, are addressed. Techniques to apply this structure to continuous-time and sampled-data analog designs are described.

https://ieeexplore.ieee.org/iel3/3910/11340/00518236.pdf

Mani Soma

Papers

Fault coverage of DC parametric tests for embedded analog amplifiers

A digital method for phase noise measurement

A reconfigurable approach to a systolic sorting architecture

Effects of deterministic jitter in a cable on jitter tolerance measurements

Structure and concepts for current-based analog scan