Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

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Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.

Jitter measuring apparatus, jitter measuring method and PLL circuit

This paper proposes a method to measure the center frequency and bandwidth of a radio-frequency front-end circuit using the peak amplitudes and the period of the output signal in response to a realistic step-input signal. The method is suitable for implementation in external test instrumentation or on chip

Method to measure RF transceiver bandwidth in the time domain

There is provided a jitter estimating apparatus for calculating phase noise waveform of an input signal and for estimating a peak value, a peak-to-peak value and a worst value of jitter of the input signal, and probability to generate jitter based on the phase noise waveform. Timing jitter sequence, period jitter sequence, and cycle to cycle period jitter sequence of the input signal are calculated and the peak value and the peak to peak value for each jitter, as well as probability to generate jitter may be estimated.

Jitter estimating apparatus and estimating method

This paper proposes a new method for measuring clock jitter using a delta-time-to-voltage converter. The method has been implemented in 0.11-mum CMOS technology, and has been verified experimentally to at least 2.8 GHz.

An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter

A BIST (built-in self-test)-compatible method for the design, layout, and test of structured logic arrays is presented. The layout is analyzed for realistic faults in the conducting layers of a typical CMOS process. It is found that only one-third of the faults while occurring as a result of random spot defects are classical stuck faults while others have to be manipulated by the appropriate test vectors to manifest themselves as stuck faults further down in the circuit. Many of these faults are detected by the test method adopted without any special provisions in the circuit. This technique eliminates the need for placing shift registers and exclusive-OR gates on the product lines of the array. >

Mani Soma

Papers

Jitter measuring apparatus, jitter measuring method and PLL circuit

Method to measure RF transceiver bandwidth in the time domain

Jitter estimating apparatus and estimating method

An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter

A BIST design of structured arrays with fault-tolerant layout