Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

/pdf/wireless-implantable-microsystems-high-density-electronic-2s60s28lz9.pdf

Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

Recent analog designers do think about measurement at design time. Analog design-for-measurement is a real success, not based on test research but based on designers' incorporation of calibration methods to ensure that their circuits work within specifications. In the meantime, mixed-signal test research has not kept pace with new design architectures, and some analog designers have outpaced mixed-signal test/design-for-test researchers. This session will elucidate the key factors for this success and the differences between design and test. And the session will discusses a designers' and test researchers' roles on analog design-for-test from each viewpoint, and some challenges on collaborating designers and test researchers.

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Fields produced by the cochlear prosthesis

This paper presents the design of a mixed digital/analog array to implement several signal processing algorithms used in coordinate rotation for image processing. The advantages of hybrid arrays in which the processor element can be either analog or digital depending on a specific computing requirement are discussed. The interfaces between processor elements of different types are considered and several circuits are designed for this task. The proposed mixed array architecture is shown to possess strong potential in other high-performance computing applications.© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Mixed digital/analog VLSI array architectures for image processing

http://link.springer.com/content/pdf/10.1007/978-94-009-9556-7_27.pdf

Integrated Circuit Technology and the Realization of an Implantable Auditory Prosthesis

A new design for a mismatch-tolerant on-chip data jitter measurement circuit in 0.11-mum CMOS is experimentally verified in this paper. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The circuit's tolerance to data-rate changes is verified using 2.5 Gbps and 2.98 Gbps PRBS signals. The jitter gain of the prototype circuit is also shown to be less sensitive to variations in the supply voltage.

Mani Soma

Papers

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Fields produced by the cochlear prosthesis

Mixed digital/analog VLSI array architectures for image processing

Integrated Circuit Technology and the Realization of an Implantable Auditory Prosthesis

Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter