Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

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Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

A processing apparatus for processing an electronic device having a light emitting unit, includes: a light receiving unit for receiving light emitted by the light emitting unit; a position detector for detecting the position of the electronic device; and a processing unit for processing the electronic device based on the position of the electronic device detected by the position detector.

Processing apparatus, processing method and position detecting device

A jitter measurement apparatus for measuring a jitter of a signal under measurement includes: a delay circuit which generates a delayed signal that is delayed from the signal under measurement by a predetermined delay time; and a phase detector which detects an instantaneous phase error between the signal under measurement and the delayed signal.

Jitter measurement apparatus and jitter measurement method

In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced.

Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures

Fast and efficient test generation techniques are key to reducing the current high cost of testing analog circuits. A new multi-frequency test generation technique for detecting catastrophic failures in this class of circuits is presented. Testability transfer factors are introduced and we use them to construct an efficient test set for analog circuits. Fault detectability and fault coverage are also defined. Two circuits from the suite of analog and mixed-signal benchmark circuits are used to validate our approach.

Testability analysis and multi-frequency ATPG for analog circuits and systems

An input clock signal is transformed into a complex analytic signal z c (t) by an analytic signal transforming means 13 and an instantaneous phase of its real part x c (t) is estimated using the analytic signal z c (t). A linear phase is removed from the instantaneous phase to obtain a phase noise waveform Δφ(t). A peak value Δφ max of absolute values of the Δφ(t) is obtained, and 4Δφ max is defined as the worst value of period jitter of the input signal. The Δφ(t) is sampled at a timing close to a zero-crossing point of the x c (t) to extract the sample value. A differential between adjacent samples is obtained in the sequential order to calculate a root-mean-square value of the differentials (period jitters). An exp(−(2Δφ max ) 2 /(2σ j 2 )) is calculated from the mean-square value σ j and 2Δφ max , and the calculated value is defined as a probability that a period jitter exceeds 2Δφ max .

Mani Soma

Papers

Processing apparatus, processing method and position detecting device

Jitter measurement apparatus and jitter measurement method

Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures

Testability analysis and multi-frequency ATPG for analog circuits and systems

Apparatus for and method of measuring a peak jitter