Fast Fourier Transform

Resonance-based wireless power delivery is an efficient technique to transfer power over a relatively long distance. This technique typically uses four coils as opposed to two coils used in conventional inductive links. In the four-coil system, the adverse effects of a low coupling coefficient between primary and secondary coils are compensated by using high-quality (Q) factor coils, and the efficiency of the system is improved. Unlike its two-coil counterpart, the efficiency profile of the power transfer is not a monotonically decreasing function of the operating distance and is less sensitive to changes in the distance between the primary and secondary coils. A four-coil energy transfer system can be optimized to provide maximum efficiency at a given operating distance. We have analyzed the four-coil energy transfer systems and outlined the effect of design parameters on power-transfer efficiency. Design steps to obtain the efficient power-transfer system are presented and a design example is provided. A proof-of-concept prototype system is implemented and confirms the validity of the proposed analysis and design techniques. In the prototype system, for a power-link frequency of 700 kHz and a coil distance range of 10 to 20 mm, using a 22-mm diameter implantable coil resonance-based system shows a power-transfer efficiency of more than 80% with an enhanced operating range compared to ~40% efficiency achieved by a conventional two-coil system.

Design and Optimization of Resonance-Based Efficient Wireless Power Delivery Systems for Biomedical Implants

This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease.

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Wireless implantable microsystems: high-density electronic interfaces to the nervous system

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Design and Optimization of Printed Spiral Coils for Efficient Transcutaneous Inductive Power Transmission

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

This paper describes a framework of strategies and structures to provide test access to mixed analog-digital MCMs. Recognizing that these mixed-signal devices contain a wide variety of components (from passive to active, from ASICs to off-the-shelf parts), the strategies presented include hierarchies of test access, and circuits to implement them. Frequently used structures such as the classical multiplexers and IEEE Std. 1149.1 are integrated with new structures more suitable for analog and mixed-signal test, such as current-based analog scan and IEEE P1149.4. Five general access circuit types and four major control topologies are described taking into account the requirements for test accuracy and the tradeoffs involved in design and test.

Strategies and structures for test access in mixed-signal MCMs

Is it possible to create analog fault models that are theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements? This presentation challenges the audience to face this question heads-on, given the variety of analog fault models in use in the past twenty years. We will review various efforts, from those relying on mapping manufacturing defects to devices and circuits to others relying on process variations, block-level parametric variations, and circuit-level specification variations. While the impediments to the development of a standard analog fault model are obvious, the procedures to create such a model have never been elucidated, always left as future work to be done later. Well, the future is now. The presentation, with audience participation, seeks to outline possible procedures to solve this problem defined in the past yet still continuing to affect current and future technologies.

Analog fault models: Back to the future?

This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent-time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.

An equivalent-time and clocked approach for continuous-time quantization

Jitter-Measurement Circuit without a Reference-Clock Input

A signal under measurement is converted into a complex analysis signal by using Hilbert transform, and the instantaneous phase of the signal under measurement is estimated from the complex analysis signal. The least-square line of the instantaneous phase is determined to determine the linear instantaneous phase of the signal under measurement. The zero-cross timing of the signal under measurement is estimated by interpolation. The difference at the zero-cross timing between the instantaneous phase value and the linear instantaneous phase value is determined to estimate a timing jitter series, and the jitter of the signal under measurement is determined from the jitter series.

Mani Soma

Papers

Strategies and structures for test access in mixed-signal MCMs

Analog fault models: Back to the future?

An equivalent-time and clocked approach for continuous-time quantization

Jitter-Measurement Circuit without a Reference-Clock Input

Jitter measuring apparatus, jitter measuring method, and tester