다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Contents: Variety and Quality. Variability loss and tolerance. Determining tolerances. Tolerance design and experimental design. Offline and online quality control. Parameter design and tolerance design: case study. Experimental design for smaller is better characteristics. Experimental design for larger is better characteristics. Bypassing the S/N ratio: spring experiment. Experimental design for dynamic characteristics.

Introduction to quality engineering. designing quality into products a

Semiconductor Power Devices

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

Superjunction Power Devices, History, Development, and Future Prospects

A method of fabricating a semiconductor device includes preparing a semiconductor wafer having a top surface and a bottom surface. The semiconductor wafer is loaded onto a wafer chuck, and the bottom surface of the loaded semiconductor wafer faces the wafer chuck. A groove is formed in the top surface of the loaded semiconductor wafer by irradiating a second laser onto the top surface, and a reforming region is formed in the loaded semiconductor wafer under the groove by irradiating a first laser through wafer chuck and bottom surface of the semiconductor wafer into a region in which the first laser is focused. The semiconductor wafer is unloaded from the wafer chuck. The bottom surface of the semiconductor wafer is ground to decrease a thickness of the semiconductor wafer. The semiconductor wafer is separated along the groove and the reforming region, thereby forming a plurality of unit chips.

Method of Fabricating Semiconductor Device

An integrated circuit ( 200 ) includes one of more transistors ( 210 ) on or in a substrate ( 10 ) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor ( 210 ). The DEMOS transistor includes a drift region ( 14 ) in the surface layer having a first dopant type, a field dielectric ( 23 ) in or on a portion of the surface layer, and a body region of a second dopant type ( 16 ) within the drift region ( 14 ). The body region ( 16 ) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric ( 21 ) is on at least a portion of the body wall. An electrically conductive gate electrode ( 22 ) is on the gate dielectric ( 21 ) on the body wall. A source region ( 18 ) of the first doping type is in the body region ( 16 ), a drain region ( 20 ) of the first doping type is in the drift region ( 14 ), and interconnects ( 521 ) are operable to electrically connect the one or more transistors to each other on the integrated circuit ( 200 ).

Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

Moving current filaments in integrated DMOS transistors under short-duration current stress

In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineon's SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices.

Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures

A 2-terminal (i.e., anode, cathode) symmetrical bi-directional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bi-directional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bi-directional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.

Symmetrical bi-directional semiconductor esd protection device

A physics-based analytical model for the on-resistance in the linear transport regime and its application as an alternative tool for the investigation of the hot-carrier stress degradation in shallow-trench-isolation-based laterally diffused MOS devices are presented. The extraction of the model and its validation by comparison with experimental and TCAD data are reported. A thorough investigation of the degradation under low- and high-gate stress biases, corresponding to saturation and impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependences of the parameter drifts.

Marie Denison

Papers

Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric

Moving current filaments in integrated DMOS transistors under short-duration current stress

Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures

Symmetrical bi-directional semiconductor esd protection device

Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors