다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

There is a special reason for reviewing this book at this time: it is the 50th edition of a compendium that is known and used frequently in most chemical and physical laboratories in many parts of the world. Surely, a publication that has been published for 56 years, withstanding the vagaries of science in this century, must have had something to offer. There is another reason: while the book is a standard fixture in most chemical and physical laboratories, including those in medical centers, it is not as frequently seen in the laboratories of physician's offices (those either in solo or group practice). I believe that the Handbook can be useful in those laboratories. One of the reasons, among others, is that the various basic items of information it offers may be helpful in new tests, either physical or chemical, which are continuously being published. The basic information may relate

Handbook of Chemistry and Physics

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

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In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.

Theory of the Junctionless Nanowire FET

It is shown that the universal set of quantum logic gates can be realized using solid-state quantum bits based on coherent electron transport in quantum wires. The elementary quantum bits are realized with a proper design of two quantum wires coupled through a potential barrier. Numerical simulations show that (a) a proper design of the coupling barrier allows one to realize any one-qbit rotation and (b) Coulomb interaction between two qbits of this kind allows the implementation of the CNOT gate. These systems are based on a mature technology and seem to be integrable with conventional electronics.

/pdf/quantum-logic-gates-based-on-coherent-electron-transport-in-2zs9sc3sx3.pdf

Quantum logic gates based on coherent electron transport in quantum wires.

In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 /spl mu/m. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort.

A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

Susanna Reggiani

Papers

Theory of the Junctionless Nanowire FET

Quantum logic gates based on coherent electron transport in quantum wires.

A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs