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Mark Beaverton Doczy
Researcher at Intel
Publications - 18
Citations - 2721
Mark Beaverton Doczy is an academic researcher from Intel. The author has contributed to research in topics: MOSFET & CMOS. The author has an hindex of 13, co-authored 18 publications receiving 2666 citations.
Papers
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Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.
Journal ArticleDOI
High performance fully-depleted tri-gate CMOS transistors
Brian S. Doyle,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Anand Portland Murthy,Rafael Rios,R. Chau +9 more
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.
Journal ArticleDOI
High-/spl kappa//metal-gate stack and its MOSFET characteristics
TL;DR: In this paper, the authors show that surface phonon scattering in the high/spl kappa/ dielectric is the primary cause of channel electron mobility degradation, and demonstrate that metal-gate electrodes, such as the ones with n+ and p+ work functions, are effective in improving channel mobilities to close to those of the conventional SiO/sub 2/poly-Si stack.
Proceedings ArticleDOI
Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout
B. Doyle,Boyan Boyanov,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Rafael Rios,R. Chau +9 more
TL;DR: In this article, the Tri-Gate body dimensions are compared to single-gate or double-gate devices, and the corner plays a fundamental role in determining the device I-V characteristics.
Proceedings ArticleDOI
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
Jack Portland Kavalieros,B. Doyle,Suman Datta,G. Dewey,Mark Beaverton Doczy,B. Jin,D. Lionberger,Matthew V. Metz,Willy Rachmady,Marko Radosavljevic,Uday Shah,Nancy M. Zelick,R. Chau +12 more
TL;DR: In this paper, the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering are combined with high performance NMOS and PMOS trigate transistors.