All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Nanowire transistors without junctions

Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs

A Graphene Field-Effect Device

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

/pdf/high-performance-fully-depleted-tri-gate-cmos-transistors-2r4lid2a28.pdf

High performance fully-depleted tri-gate CMOS transistors

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

http://www.ndcl.ee.psu.edu/papers/31_Kavalieros_Datta_VLSI%202006.pdf

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

http://www.ndcl.ee.psu.edu/papers/28_Chau_INFOS_2005_Micro_Engg.pdf

B. Jin

Papers

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

High performance fully-depleted tri-gate CMOS transistors

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology