There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Wireless indoor positioning systems have become very popular in recent years. These systems have been successfully used in many applications such as asset tracking and inventory management. This paper provides an overview of the existing wireless indoor positioning solutions and attempts to classify different techniques and systems. Three typical location estimation schemes of triangulation, scene analysis, and proximity are analyzed. We also discuss location fingerprinting in detail since it is used in most current system or solutions. We then examine a set of properties by which location systems are evaluated, and apply this evaluation method to survey a number of existing systems. Comprehensive performance comparisons including accuracy, precision, complexity, scalability, robustness, and cost are presented.

Survey of Wireless Indoor Positioning Techniques and Systems

National Institute of Standards and Technology における超伝導研究及び生活

We present a new block cipher LED. While dedicated to compact hardware implementation, and offering the smallest silicon footprint among comparable block ciphers, the cipher has been designed to simultaneously tackle three additional goals. First, we explore the role of an ultra-light (in fact non-existent) key schedule. Second, we consider the resistance of ciphers, and LED in particular, to related-key attacks: we are able to derive simple yet interesting AES-like security proofs for LED regarding related- or single-key attacks. And third, while we provide a block cipher that is very compact in hardware, we aim to maintain a reasonable performance profile for software implementation.

The LED block cipher

In this paper we propose a new family of very efficient hardware oriented block ciphers. The family contains six block ciphers divided into two flavors. All block ciphers share the 80-bit key size and security level. The first flavor, KATAN, is composed of three block ciphers, with 32, 48, or 64-bit block size. The second flavor, KTANTAN, contains the other three ciphers with the same block sizes, and is more compact in hardware, as the key is burnt into the device (and cannot be changed).

The smallest cipher of the entire family, KTANTAN32, can be implemented in 462 GE while achieving encryption speed of 12.5 KBit/sec (at 100 KHz). KTANTAN48, which is the version we recommend for RFID tags uses 588 GE, whereas KATAN64, the largest and most flexible candidate of the family, uses 1054 GE and has a throughput of 25.1 Kbit/sec (at 100 KHz).

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KATAN and KTANTAN -- A Family of Small and Efficient Hardware-Oriented Block Ciphers

Globally Asynchronous Locally Synchronous (GALS) is a paradigm for complexity management and re-use of large System-on-Chip (SoC) architectures. GALS is most often based on specific ASIC design components or special FPGA platforms with custom development tools. In this paper we present a multiprocessor GALS implementation on a standard commercial FPGA with standard development tools. The key building block is a novel, reliable RTL mixed clock FIFO. A complete MPEG-4 video encoder with four processors is implemented for proofing the concept. The area overhead compared to a fully synchronous design is shown to be only 2% and the performance overhead is 3%. This is negligible compared to the benefits that are much better flexibility, ASIC or FPGA vendor independency, and reduced design time. Furthermore, the mixed-clock interfaces allow easy re-usability, since the RTL-level blocks do not need to be re-verified in design iterations.

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, which has been standardized by ISO/IEC and evaluated in the European research project NESSIE. In this paper we present a Whirlpool hashing hardware core suited for devices in which low cost is desired. The core constitutes of a novel 8-bit architecture that allows compact realizations of the algorithm. In the Xilinx Virtex-II Pro XC2VP40 FPGA, our implementation consumes 376 slices and achieves the throughput of 81.5 Mbit/s. The resource utilization of our design is one fourth of the smallest Whirlpool implementation presented to date.

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Compact hardware design of Whirlpool hashing core

The diversity of applications, scarce resources, and large scale set demanding requirements for Wireless Sensor Networks (WSN). All requirements cannot be fulfilled by a general purpose WSN, but a development of application specific WSNs is needed. We present a novel WIreless SEnsor NEtwork Simulator (WISENES) framework for rapid design, simulation, evaluation, and implementation of both single nodes and large WSNs. New WSN design starts from high level Specification and Description Language (SDL) model, which is simulated and implemented on a prototype through code generation. One of the novel features is the back-annotation of measured values from physical prototypes to SDL model. The scalability and performance of WISENES have been evaluated with TUTWSN that is a very energy efficient new WSN. The results show only 6.7 percent difference between modeled and measured TUTWSN prototype energy consumption. Thus, WISENES hastens the development of WSN protocols and their evaluation in large networks.

High abstraction level design and implementation framework for wireless sensor networks

This paper presents the analysis and real experiments on TCP/IP communication in a low-power monitoring Wireless Sensor Network (WSN). TCP/IP flow control, addressing, and packet fragmentation are adapted in a gateway that relays TCP/IP communication to WSN. The performance of TCP/IP is evaluated between endpoint PCs communicating over TUTWSN (Tampere University of Technology WSN), which is used as a transparent communication medium for TCP/IP data. The evaluation results show that the window-based flow control algorithms of TCP perform too aggressively in WSNs, where random bit errors and topology changes are main reasons for errors instead of congestion. Further, a frequent duty cycle is needed in WSN to compensate the TCP/IP overhead. In TUTWSN, compared to an environmental monitoring application with two second activity cycle and native WSN transport, the enabling of TCP/IP consumes five times more power.

Experimenting TCP/IP for Low-Power Wireless Sensor Networks

This paper introduces the architecture of a base station designed for a new Wireless Local Area Network (WLAN). The emphasis is on the software but also backgrounds for the design choices made are discussed. The main design objective has been to develop a simple and low-cost system while maintaining suitability for a large variety of applications, ranging from wireless sensors to multimedia workstations. A base station is implemented by attaching a custom WLAN adapter card into a PC. The network adapter consists of a custom wireless Medium Access Control (MAC) protocol and a standard low-power radio subsystem. The PC hosts other wireless network related functions, such as management of a wireless cell and bridging of data between the wireless network and a wired LAN. Currently, a demonstrator network is being implemented. Components implemented for a base station contain the network adapter card, a Windows NT device driver, and a management application that is a user mode program needed for configuring and managing the network interface hardware and the MAC protocol. In addition, a Windows NT protocol driver has been developed for implementing the data exchange between the device driver and the management application.

Marko Hännikäinen

Papers

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

Compact hardware design of Whirlpool hashing core

High abstraction level design and implementation framework for wireless sensor networks

Experimenting TCP/IP for Low-Power Wireless Sensor Networks

Windows NT software design and implementation for a wireless LAN base station