Compact hardware design of Whirlpool hashing core
Timo Alho,Panu Hämäläinen,Marko Hännikäinen,Timo Hämäläinen +3 more
- pp 1247-1252
TLDR
A Whirlpool hashing hardware core suited for devices in which low cost is desired, and constitutes of a novel 8-bit architecture that allows compact realizations of the algorithm.Abstract:
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, which has been standardized by ISO/IEC and evaluated in the European research project NESSIE. In this paper we present a Whirlpool hashing hardware core suited for devices in which low cost is desired. The core constitutes of a novel 8-bit architecture that allows compact realizations of the algorithm. In the Xilinx Virtex-II Pro XC2VP40 FPGA, our implementation consumes 376 slices and achieves the throughput of 81.5 Mbit/s. The resource utilization of our design is one fourth of the smallest Whirlpool implementation presented to date.read more
Citations
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Journal ArticleDOI
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
TL;DR: This work evaluates and compares the effectiveness of common hiding countermeasures against DPA in FPGA-based designs, using the Whirlpool hash function as a case study and develops a new design flow called Isolated WDDL (IWDDL).
Proceedings ArticleDOI
ASIC hardware implementations for 512-bit hash function Whirlpool
TL;DR: Hardware architectures for the 512-bit hash function Whirlpool, which is one of the ISO/IEC 10118-3 standard algorithms, are proposed and the performances of the proposed architectures are evaluated using a 0.18-mum CMOS standard cell library.
Journal ArticleDOI
Research of Integrity and Authentication in OPC UA Communication Using Whirlpool Hash Function
TL;DR: A new security communication model to provide integrity and authentication in OPC UA is proposed, which uses the Whirlpool hash function to check integrity and generates digital signature along with RSA in message transmission.
Proceedings ArticleDOI
General-purpose FPGA platform for efficient encryption and hashing
TL;DR: This paper proposes reconfigurable FPGA hardware components that enable rapid deployment of cryptographic and other algorithms, and achieves the best efficiency in Mbps/slice for Whirlpool.
Proceedings ArticleDOI
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
TL;DR: In this paper, several hardware architectures of RadioGatun and irRUPT have been investigated for achieving high throughputs with minimal area occupation, and the IRUPUT core achieves 2.4 Gbps (with long input messages) on ASIC, and 1.1 Gbps on FPGA.
References
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