Marta Bagatin

TL;DR: A comprehensive discussion of total dose and single event effects results is presented in this paper concerning both floating gate cells and peripheral circuitry, including new findings on the mechanism underlying upsets due to heavy ions and destructive events.

TL;DR: A new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA is introduced.

TL;DR: This contribution analyzes TID effects on the many different building blocks of NAND Flash memories, including the charge pumps, row-decoder, and floating gate array, and identifies and study the characteristic failure mode for each part.

TL;DR: In this paper, the authors present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing.

TL;DR: The dependence of annealing on the program level is investigated, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell, to understand the underlying physics.