Numonyx

About: Numonyx is a based out in . It is known for research contribution in the topics: Flash memory & Non-volatile memory. The organization has 266 authors who have published 201 publications receiving 4727 citations.

Monolithic germanium/silicon avalanche photodiodes with 340 GHz gain-bandwidth product

Abstract: Significant progress has been made recently in demonstrating that silicon photonics is a promising technology for low-cost optical detectors, modulators and light sources1,2,3,4,5,6,7,8,9,10,11,12. It has often been assumed, however, that their performance is inferior to InP-based devices. Although this is true in most cases, one of the exceptions is the area of avalanche photodetectors, where silicon's material properties allow for high gain with less excess noise than InP-based avalanche photodetectors and a theoretical sensitivity improvement of 3 dB or more. Here, we report a monolithically grown germanium/silicon avalanche photodetector with a gain–bandwidth product of 340 GHz, a keff of 0.09 and a sensitivity of −28 dB m at 10 Gb s−1. This is the highest reported gain–bandwidth product for any avalanche photodetector operating at 1,300 nm and a sensitivity that is equivalent to mature, commercially available III–V compound avalanche photodetectors. This work paves the way for the future development of low-cost, CMOS-based germanium/silicon avalanche photodetectors operating at data rates of 40 Gb s−1 or higher. A monolithically grown Ge/Si avalanche photodetectors (APD) with a gain–bandwidth product of 340 GHz, the highest value for any APDs operating at 1,300 nm, and a sensitivity equivalent to commercially available III-V compound APDs is reported. The excellent performance paves the way to achieving low-cost, CMOS-based, Ge/Si APDs operating at data rates of 40 Gb s−1 or higher, where the performance of III-V APDs is severely limited.

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

Abstract: In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge2-Sb2-TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.

A stackable cross point Phase Change Memory

Abstract: A novel scalable and stackable nonvolatile memory technology suitable for building fast and dense memory devices is discussed. The memory cell is built by layering a storage element and a selector. The storage element is a Phase Change Memory (PCM) cell [1] and the selector is an Ovonic Threshold Switch (OTS) [2]. The vertically integrated memory cell of one PCM and one OTS (PCMS) is embedded in a true cross point array. Arrays are stacked on top of CMOS circuits for decoding, sensing and logic functions. A RESET speed of 9 nsec and endurance of 106 cycles are achieved. One volt of dynamic range delineating SET vs. RESET is also demonstrated.

Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories

Abstract: This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.

Wavelength Division Multiplexing Based Photonic Integrated Circuits on Silicon-on-Insulator Platform

Abstract: We review recent advances in the development of silicon photonic integrated circuits for high-speed and high-capacity interconnect applications. We present detailed design, fabrication, and characterization of a silicon integrated chip based on wavelength division multiplexing. In such a chip, an array of eight high-speed silicon optical modulators is monolithically integrated with a silicon-based demultiplexer and a multiplexer. We demonstrate that each optical channel operates at 25 Gb/s. Our measurements suggest the integrated chip is capable of transmitting data at an aggregate rate of 200 Gb/s. This represents a key milestone on the way for fabricating terabit per second transceiver chips to meet the demand of future terascale computing.