Showing papers by "Massoud Pedram published in 2010"
18 Aug 2010
TL;DR: This work introduces a HEES (hybrid EES) system comprising heterogeneous EES elements and builds on the concepts of computer memory system architecture and management in order to achieve the attributes of an ideal EES system through appropriate allocation and organization of various types of Ees elements.
Abstract: Electrical energy is a high quality form of energy that can be easily converted to other forms of energy with high efficiency and, even more importantly, it can be used to control lower grades of energy quality with ease. However, building a cost-effective electrical energy storage (EES) system is a challenging task despite steady advances in the design and manufacturing of EES elements including various battery and supercapacitor technologies. As of today, no single type of EES element fulfills high energy density, high power delivery capacity, low cost per unit of storage, long cycle life, low leakage, and so on at the same time. Unlike conventional EES systems, we introduce a HEES (hybrid EES) system comprising heterogeneous EES elements. Our proposed HEES system builds on the concepts of computer memory system architecture and management in order to achieve the attributes of an ideal EES system through appropriate allocation and organization of various types of EES elements. We also introduce a HEES design considerations which should be taken into account to optimize the amortized cost for the system, including the initial cost (cost per capacity), the operating cost (efficiency), the maintenance cost (cycle life and disposal cost), and so forth.
119 citations
08 Mar 2010
TL;DR: This paper describes one such approach where a PTM engine decides on the number and placement of ON servers while simultaneously adjusting the supplied cold air temperature, and demonstrates the effectiveness of the proposed dynamic resource provisioning method.
Abstract: The current energy and environmental cost trends of datacenters are unsustainable. It is critically important to develop datacenter-wide power and thermal management (PTM) solutions that improve the energy efficiency of the datacenters. This paper describes one such approach where a PTM engine decides on the number and placement of ON servers while simultaneously adjusting the supplied cold air temperature. The goal is to minimize the total power consumption (for both servers and air conditioning units) while meeting an upper bound on the maximum temperature seen in any server chassis in the data center. To achieve this goal, it is important to be able to predict the incoming workload in terms of requests per second (which is done by using a short-term workload forecasting technique) and to have efficient runtime policies for bringing new servers online when the workload is high or shutting them off when the workload is low. Datacenter-wide power saving is thus achieved by a combination of chassis consolidation and efficient cooling. Experimental results demonstrate the effectiveness of the proposed dynamic resource provisioning method. 1
112 citations
TL;DR: Experimental results demonstrate that the proposed supervised learning based power management technique ensures system-wide energy savings under rapidly and widely varying workloads.
Abstract: This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the occupancy state of a global service queue) and then uses this predicted state to look up the optimal power management action (eg, voltage-frequency setting) from a precomputed policy table The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce the overhead of the PM which has to repetitively determine and assign voltage-frequency settings for each processor core in the system Experimental results demonstrate that the proposed supervised learning based power management technique ensures system-wide energy savings under rapidly and widely varying workloads
109 citations
18 Aug 2010
TL;DR: This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors.
Abstract: Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.
102 citations
18 Aug 2010
TL;DR: This paper is the first paper to optimize the efficiency of a supercapacitor charging process by utilizing the MPPT technique and simultaneously considering the variable charger efficiency.
Abstract: It is important to maintain high efficiency when charging electrical energy storage elements so as to achieve holistic optimization from an energy generation source (e.g., a solar cell array) to an energy storage element (e.g., a supercapacitor bank). Previous maximum power point tracking (MPPT) methods do not consider the fact that efficiency of the charger varies depending on the power output level of the energy generation source and the state of charge of the storage element. This paper is the first paper to optimize the efficiency of a supercapacitor charging process by utilizing the MPPT technique and simultaneously considering the variable charger efficiency. More precisely, previous MPPT methods only maximize the power output of the energy generation source, but they do not guarantee the maximum energy is stored in the energy storage element. Note that the load device takes its energy from the storage element so it is important to maximize energy transfer from the source into the storage element. We present a rigorous framework to determine the optimal capacitance of a supercapacitor and optimal configuration of a solar cell array so as to maximize the efficiency of energy transfer from the solar cells into a bank of supercapacitors. Experimental results show the efficacy of the proposed technique and design optimization framework.
89 citations
04 Nov 2010
TL;DR: This paper mathematically formulate the electrical energy bill minimization problem for cooperative networked consumers who have a single energy bill, such as those working in a commercial/industrial building.
Abstract: Dynamic energy pricing is a promising development that addresses the concern of finding an environmentally friendly solution to meeting energy needs of customers while minimizing their electrical energy bill. In this paper, we mathematically formulate the electrical energy bill minimization problem for cooperative networked consumers who have a single energy bill, such as those working in a commercial/industrial building. The idea is to schedule user requests for appliance use at different times during a fixed interval based on dynamic energy prices during that interval. Two different methods are presented to minimize the energy cost of such users under non-interruptible or interruptible jobs. The methods relay on a quasi-dynamic pricing function for unit of energy consumed, which comprises of a base price and a penalty term. The methods minimize the energy cost of the users while meeting all the scheduling constraints and heeding the pricing function. The proposed methods result in significant savings in the energy bill under different usage pricing, and scheduling constraints.
71 citations
13 Sep 2010
TL;DR: Based on extensive experiments and measurements, accurate power and performance models for a high performance multi-core server system with virtualization are presented.
Abstract: Virtualization has become a very important technology which has been adopted in many enterprise computing systems and data centers. Virtualization makes resource management and maintenance easier, and can decrease energy consumption through resource consolidation. To develop and employ sophisticated resource management, accurate power and performance models of the hardware resources in a virtualized environment are needed. Based on extensive experiments and measurements, this paper presents accurate power and performance models for a high performance multi-core server system with virtualization.
70 citations
22 Mar 2010
TL;DR: The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level to demonstrate the high efficacy of the proposed hierarchical PM framework.
Abstract: In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power consumption of a Chip Multiprocessor (CMP) while maintaining a target average throughput. The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level. Our experimental results are very favorable showing noticeable average power saving compared to a baseline technique, and demonstrate the high efficacy of the proposed hierarchical PM framework.
35 citations
03 Aug 2010
TL;DR: This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput by developing a three-level hierarchical framework comprised of a control theory-based dynamic power manager (DPM) and a task assignment unit.
Abstract: This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput. The minimum energy solution subject to a throughput constraint is achieved by selectively turning cores ON or OFF, assigning a given set of tasks to different cores, and simultaneously selecting the optimum operating supply voltage and clock frequency level for each processor core in the system. This NP-hard problem is solved by a three-level hierarchical framework comprised of a control theory-based dynamic power manager (DPM) and a task assignment unit. Experimental results demonstrate 17% energy saving of the proposed solution approach.
20 citations
22 Mar 2010
TL;DR: It is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design and an efficient algorithm is introduced for characterizing the codependent setup andHold time (CSHT) contours.
Abstract: With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing the codependent setup and hold time (CSHT) contours. Third, we introduce a multi- corner optimization problem to minimize the energy-delay product of the flip-flops. The optimization relies on mathematical programming to find the best transistor sizes. Finally, we apply our proposed optimization formulation on True Single-Phase Clock (TSPC) flip-flops and show the simulation results.1
13 citations
TL;DR: In this article, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed, which operates under a wide range of input and output voltages, makes use of a statedependent hysteretic comparator.
Abstract: In this paper, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed. The converter, which operates under a wide range of input and output voltages, makes use of a statedependent hysteretic comparator. Depending on the output current, the converter automatically changes the operating mode. This improves the efficiency and reduces the output voltage ripple for a wide range of output currents for given input and output voltages. The sensitivity of the output voltage to the circuit elements is less than 14%, which is seven times lower than that for conventional converters. To assess the efficiency of the proposed converter, it is designed and implemented with commercially available components. The converter provides an output voltage in the range of 0.9V to 31V for load currents of up to 3A when the input voltage is in the range of 5V to 32V. Analytical design expressions which model the operation of the converter are also presented. This circuit can be implemented easily in a single chip with an external inductor and capacitor for both fixed and variable output voltage applications.
08 Mar 2010
TL;DR: A rigorous and robust foundation to mathematically model output waveforms under sources of variability and to compress the library data is introduced and experimental results demonstrate the effectiveness of the proposed variational CSM modeling framework and the stratification-based compression approach.
Abstract: In deep sub-micron technology, accurate modeling of output waveforms of library cells under different input slew and load capacitance values is crucial for precise timing and noise analysis of VLSI circuits. Construction of a compact and efficient model of such waveforms becomes even more challenging when manufacturing process and environmental variations are considered. This paper introduces a rigorous and robust foundation to mathematically model output waveforms under sources of variability and to compress the library data. The proposed approach is suitable for today's current source model (CSM) based ASIC libraries. It employs an orthonormal transformation to represent the output waveforms as a linear combination of some appropriately-derived basis waveforms. More significantly Robust Principle Component Analysis (RPCA) is used to stratify the library waveforms into a small number of groups for which different sets of principle components are calculated. This stratification results in a very high compression ratio for the variational CSM library while meeting a maximum error tolerance. Interpolation and further compression is obtained by representing the coefficients as signomial functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. We propose a procedure to calculate the coefficients and power of the signomial functions. Experimental results demonstrate the effectiveness of the proposed variational CSM modeling framework and the stratification-based compression approach.
TL;DR: The optimized ECC processor performs a single 192-bit scalar multiplication in 652ms consuming only 22.3µJ at a clock frequency of 1MHz, indicating a 13% reduction in the energy and power consumption compared to the previously reported design.
Abstract: This paper presents a low-energy prime-field elliptic-curve cryptography (ECC) hardware processor, suitable for low-power and/or energy-efficient applications and systems. The ECC processor is obtained by power-optimizing a previously reported design. The optimization is performed by making the power consumption profile of the processor as uniform as possible, in an attempt to increase the secondary battery life between discharge and recharge cycles and to create resistance against simple power attacks (SPA) to the cryptosystem by analyzing the power dissipation trace of the hardware. The optimized ECC processor performs a single 192-bit scalar multiplication in 652ms consuming only 22.3µJ at a clock frequency of 1MHz. This indicates, in addition to the more uniform power consumption, a 13% reduction in the energy and power consumption compared to the previously reported design.
08 Mar 2010
TL;DR: Simulation results demonstrate that the proposed technique ensures energy savings, while satisfying design goals in terms of total PDN cost and its power efficiency.
Abstract: With the increasing demand for energy-efficient power delivery network (PDN) in today's electronic systems, configuring an optimal PDN that supports power management techniques, e.g., dynamic voltage scaling (DVS), has become a daunting, yet vital task. This paper describes how to model and configure such a PDN so as to minimize the total energy dissipation in DVS-enabled systems, while satisfying total PDN cost and/or power conversion efficiency constraints. The problem of configuring an energy-efficient PDN under various constraints is subsequently formulated by using a controllable Markovian decision process (MDP) model and solved optimally as a policy optimization problem. The key rationale for utilizing MDP for solving the PDN configuration problem is to manage stochastic behavior of the power mode transition times of DVS-enabled systems. Simulation results demonstrate that the proposed technique ensures energy savings, while satisfying design goals in terms of total PDN cost and its power efficiency.1
TL;DR: An on-line adaptive policy is proposed, which dynamically monitors the channel conditions and the server behavior, takes into account real-time constraints, and adopts a client-side power management policy with task migration that results in optimum energy consumption in the client.
Abstract: This paper addresses the problem of extending the lifetime of a battery-powered mobile host in a client-server wireless network by using task migration and remote processing. This problem is solved by first constructing a stochastic model of the client-server system based on the theory of continuous-time Markovian decision processes. Next the dynamic power management problem with task migration is formulated as a policy optimization problem and solved exactly by using a linear programming approach. Based on the off-line optimal policy derived in this way, an on-line adaptive policy is proposed, which dynamically monitors the channel conditions and the server behavior, takes into account real-time constraints, and adopts a client-side power management policy with task migration that results in optimum energy consumption in the client. Experimental results demonstrate that the proposed method outperforms existing heuristic methods by as much as 35% in terms of the overall energy savings.
03 Aug 2010
TL;DR: This paper presents the analysis and optimization of a flip-flop while considering the effect of energetic particle hits on its setup and hold times, and how to size transistors of a clocked master-slave CMOS flip- flop to make it more robust against single-event timing upsets.
Abstract: This paper presents the analysis and optimization of a flip-flop while considering the effect of energetic particle hits on its setup and hold times. First it is shown that the particle hit tightens the setup and hold timing constraints imposed on the flip-flop. Next it is shown how to size transistors of a clocked master-slave CMOS flip-flop to make it more robust against single-event timing upsets. Experimental results to assess the effectiveness of transistor sizing step are provided and discussed.1