Showing papers by "Matteo Sonza Reorda published in 2003"

An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor

Abstract: Instruction and data caches are well known architectural solutions that allow significant improvement in the performance of high-end processors. Due to their sensitivity to soft errors, they are often disabled in safety critical applications, thus sacrificing performance for improved dependability. In this paper, we report an accurate analysis of the effects of soft errors in the instruction and data caches of a soft core implementing the SPARC architecture. Thanks to an efficient simulation-based fault injection environment we developed, we are able to present in this paper an extensive analysis of the effects of soft errors on a processor running several applications under different memory configurations. The procedure we followed allows the precise computation of the processor failure rate when the cache is enabled even without resorting to expensive radiation experiments.

Exploiting programmable bist for the diagnosis of embedded memory cores

Abstract: This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.

A new software-based technique for low-cost fault-tolerant application

Abstract: A new software approach providing fault detection and correction capabilities by using software techniques is described. The approach is suitable for developing commercial-off-the-shelf processor-based architectures for safety-critical applications. Data and code duplications are exploited to provide fault detection and correction capabilities. Preliminary results coming from fault injection experiments support the effectiveness of the method.

Impact of data cache memory on the single event upset-induced error rate of microprocessors

Abstract: Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper.

A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories

Abstract: In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-a-chip (SoC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architecture to different memory cores. The proposed approach is compatible with the P1500 standard. A case study has been developed and demonstrates the advantages of the proposed core test strategy in terms of area overhead and test application time.

An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores

Abstract: This paper addresses the issue of diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper. The proposed solution exploits a hardware-implemented compression method that minimizes the amount of data to be transferred from the core to the ATE. The proposed solution takes into account several constraints existing in an industrial environment, such as reducing the time and area overheads required for diagnosis, and minimizing the cost of the external ATE. Experimental results are provided allowing evaluating the benefits and limitations of the adopted solution.

Introducing SW-based fault handling mechanisms to cope with EMI in embedded electronics: are they a good remedy?

Abstract: We summarize a study on the effectiveness of two software-based fault handling mechanisms in terms of detecting conducted electromagnetic interference (EMI) in microprocessors. One of these techniques deals with processor control flow checking. The second one is used to detect errors in code variables. In order to check the effectiveness of such techniques in RF ambient, an EIC 61.000-4-29 normative-compliant conducted RF-generator was implemented to inject spurious electromagnetic noise into the supply lines of a commercial off-the-shelf (COTS) microcontroller-based system. Experimental results suggest that the considered techniques present a good effectiveness to detect this type of faults, despite the multiple-fault injection nature of EMI in the processor control and data flows, which in most cases result in a complete system functional loss (the system must be reset).

Built-In Self Test of Sequential Circuits

Abstract: This chapter describes an innovative Built-In Self Test architecture based oncellular automata. The architecture is an enhancement of standard Circular Self-Test Path, and increases stuck-at fault coverage while maintaining all advantages, such as low timing intrusiveness, easy integration into design flow, at-speed testing. Cellular automaton rules are devised using the Selfish Gene algorithm, a new evolutionary algorithm based on an unorthodox view of the Darwinian theory, where the basic units of selection are genes rather than individuals. Experimental results show the effectiveness of the approach and the efficacy of the Selfish Gene algorithm.