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Showing papers by "Mehmet Kaynak published in 2013"


Journal ArticleDOI
TL;DR: In this article, the effect of a finite-size ground plane on the radiation pattern and reflection coefficient of a SiGe process integrated on-chip antenna is investigated, and a flat 77 GHz onchip strip dipole antenna integrated with a lumped LC balun circuit is designed and implemented.
Abstract: This letter investigates the effect of a finite-size ground plane on the radiation pattern and reflection coefficient of a SiGe process integrated on-chip antenna. A flat 77-GHz on-chip strip dipole antenna integrated with a lumped LC balun circuit is designed and implemented. For increased directivity, the etched silicon substrate is placed on a metal ground plate. The on-chip antenna with the LC balun circuit is connected to GSG pads for measurement purposes. The antenna is well matched at the original resonance frequency band with 7-12 GHz impedance bandwidth and 4 dBi measured gain at 85 GHz.

26 citations


Journal ArticleDOI
TL;DR: In this article, a highly sensitive 120 GHz integrated dielectric sensor in SiGe BiCMOS with back-side etching is presented, which consists of a bandpass filter using a planar resonator, a 120 GHz VCO at the input, and a power detector at the output.
Abstract: A highly sensitive 120 GHz integrated dielectric sensor in SiGe BiCMOS with back-side etching is presented. The sensor consists of a bandpass filter using a planar resonator, a 120 GHz VCO at the input, and a power detector at the output. The sensitivity of the stand-alone resonator and the sensor was tested by measuring the change in the detector output voltage and the shift in the frequency response of the resonator due to a dielectric sample placed over the resonator. Simulated and measured performance of the developed device are presented and discussed.

21 citations


Proceedings ArticleDOI
02 Jun 2013
TL;DR: In this paper, a monolithically integrated W-band low-noise-amplifier realized in an 0.13μm SiGe BiCMOS technology is presented, which utilizes a two-stage cascode topology with inductive emitter degeneration for simultaneous noise and power matching.
Abstract: In this paper, the authors present a monolithically integrated W-band low-noise-amplifier realized in an 0.13μm SiGe BiCMOS technology. The design utilizes a two-stage cascode topology, with inductive emitter degeneration for simultaneous noise and power matching. The paper identifies critical design parameters, and presents careful modeling results. Measurement results show excellent agreement with the simulations, and the circuit achieves 20 dB gain and 4 dB noise figure up to 110 GHz. To the authors' knowledge, this demonstrates the best noise performance up to date on a silicon platform in this frequency range.

17 citations


Proceedings ArticleDOI
20 Jan 2013
TL;DR: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process, optimized to minimize the RMS phase error.
Abstract: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process. All bits are digitally controlled. The 22.5° and 45° bits are based on switched low-pass network while the 90° and 180° bits are based on switching between high-pass/low-pass filters. Filters are implemented using on-chip spiral inductors and high-Q MIM capacitors. Switching functionality is obtained by isolated NMOS transistors employing resistive body floating technique. All bits are optimized to minimize the RMS phase error. Ordering of bits is optimized so as to minimize the overall insertion loss. Simulated insertion loss is 12±2 dB and RMS phase error is less than 2° over X-band frequencies.

12 citations


Proceedings ArticleDOI
28 Mar 2013
TL;DR: In this paper, a CMOS based high voltage generation circuit with very fast rise and fall time performance is presented, where the entire sub-block designs, namely ring oscillator, charge pump and the discharge resistor, are given.
Abstract: A CMOS based high voltage generation circuit with very fast rise and fall time performance is presented. The entire sub-block designs, namely ring oscillator, charge pump and the discharge resistor, are given. The rise and the fall time of the generated output voltage are characterized using both electrical and optical techniques. The results show that generation of up to 40V signal with a rise time of less than 10μs is possible. The fall time, which is also very critical specification considering the fast switching applications, strongly depends on the discharge resistor but less than 15μs fall times are achieved using 250KΩ discharge resistor with an expense of higher power consumption.

11 citations


Proceedings ArticleDOI
02 Jun 2013
TL;DR: In this paper, the authors present a 94 GHz flip-chip packaged SiGe BiCMOS LNA on a liquid-crystal-polymer (LCP) substrate, and measured results show that the packaged LNA provides 15.9 dB gain (at the same power consumption), only 1.3 dB lower than the on-wafer case.
Abstract: In this paper, the authors present for the first time a 94 GHz flip-chip packaged SiGe BiCMOS LNA on a liquid-crystal-polymer (LCP) substrate. The LNA is a custom design in a 0.13 μm SiGe BiCMOS process, and features a four stage common-emitter topology. The measured on-wafer gain equals 17.2 dB and the noise figure is below 7 dB at 94 GHz with a 3dB bandwidth of 18 GHz and a power consumption of 24 mW. For the packaging, the flip-chip technique is utilized on a flexible, light-weight LCP substrate material. Measured results show that the packaged LNA provides 15.9 dB gain (at the same power consumption), only 1.3 dB lower than the on-wafer case. These results demonstrate the suitability of the LCP as a substrate material, and the low-loss potential of the flip-chip packaging technique for millimeter-wave applications.

11 citations


Proceedings ArticleDOI
19 Dec 2013
TL;DR: In this article, the authors presented the results of some W-band power detector and wideband (IF) amplifier circuit designs made in 0.25 μm and 0.13 μm SiGe BiCMOS processes.
Abstract: This paper presents the results of some W-band power detector and wideband (IF) amplifier circuit designs made in 0.25 μm and 0.13 μm SiGe BiCMOS processes. Two 0.25 μm SiGe wideband power detector and amplifier RFICs present an NEP =1-2 pW/Hz1/2 at 85-101 GHz and s21=10-19 dB at 2-32 GHz, respectively. To the authors' knowledge, the proposed SiGe detector design reports the widest Sn bandwidth (s11≤ -10 dB 84-104 GHz) among SiGe based W-band detectors. Two 0.13 μm SiGe detector/amplifier circuits show a simulated NEP=0.2-0.9 pW/Hz1/2 at 75-100 GHz and S21= 19-21 dB at 5-30 GHz. The presented SiGe power detectors and (IF) amplifiers are targeting broadband applications such as passive imaging.

9 citations


Proceedings ArticleDOI
01 Jan 2013
TL;DR: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays, implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs.
Abstract: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays. The T/R module consists of a T/R switch, two SPDT switches, a power amplifier, a low noise amplifier, a phase shifter and a variable gain amplifier (not presented). The T/R switch, SPDT switch and the phase shifter are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum insertion loss of 2.1 dB, an isolation of 42 dB and has an input P1dB of 27.4 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band. The PA resulted in a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25 % PAE. The LNA has 1.65 dB noise figure (mean) with a gain more than 19 dB at X-Band. Lastly, the phase shifter achieves simulated RMS phase and gain errors of 1°-3.5° and 0.8-1.8 dB at X-Band.

8 citations


Proceedings ArticleDOI
28 Mar 2013
TL;DR: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays, implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs.
Abstract: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays. The T/R module consists of a T/R switch, two SPDT switches, a power amplifier, a low noise amplifier, a phase shifter and a variable gain amplifier (not presented). The T/R switch, SPDT switch and the phase shifter are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum insertion loss of 2.1 dB, an isolation of 42 dB and has an input P1dB of 27.4 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band. The PA resulted in a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25 % PAE. The LNA has 1.65 dB noise figure (mean) with a gain more than 19 dB at X-Band. Lastly, the phase shifter achieves simulated RMS phase and gain errors of 1°-3.5° and 0.8-1.8 dB at X-Band.

5 citations


Proceedings Article
19 Dec 2013
TL;DR: In this article, a review discusses recent developments of high-speed SiGe HBT technologies and their application to integrated circuits with operation frequencies above 100 GHz SiGeHBTs with maximum oscillation frequencies up to 500 GHz and CML ring oscillator delay times of 20 ps.
Abstract: This review discusses recent developments of high-speed SiGe HBT technologies and their application to integrated circuits with operation frequencies above 100 GHz SiGe HBTs with maximum oscillation frequencies up to 500 GHz and CML ring oscillator delay times of 20 ps are now possible The integration capability of the technologies is demonstrated with examples of on-chip 100 GHz RF-MEMS switches and 130 GHz antenna To verify not only performance but also reliability of the high-speed HBTs the results of long-term mixed-mode stress tests are presented Finally, examples of 240 GHz LNAs and 120 GHz transceivers demonstrate the circuit performance of advanced SiGe technologies

4 citations


Proceedings Article
08 Apr 2013
TL;DR: In this article, the authors present the design and characterization of a highly integrated, wideband on-chip radiometer, composed of a slot antenna, RF-MEMS Dicke Switch, LNA and a wideband power detector.
Abstract: This paper presents the design and characterization of a highly integrated, wideband on-chip radiometer, composed of a slot antenna, RF-MEMS Dicke Switch, LNA and a wideband power detector. The highly integrated single-chip RF front-end is dedicated for broadband sensing up to 110 GHz. Both antenna and radiometer are fabricated in a 0.25 μm SiGe BiCMOS process. The antenna design takes benefit of the back-side etched trench, offered by the technology. This is used to reduce losses due to the presence of the low resistivity silicon substrate. Additionally, the trench is specially shaped, as to improve the wideband matching of the antenna. The on-chip slot antenna design covers a wide bandwidth (70-110 GHz) with 0 dBi gain and 64% efficiency, both simulated at 94 GHz. The measured bandwidth spans 85 to 105 GHz. The W-band SiGe detector circuit has close to 20 GHz of operational bandwidth (S11≤-10 dB at 75-92 GHz) and presents a responsivity of 3-5kV/W (NEP=10-16 pW/Hz½) at 83-94 GHz.


Proceedings ArticleDOI
28 Mar 2013
TL;DR: In this article, a detailed thermo-mechanical analysis of the suspended membrane shows that the membrane shape and contact formation is strongly affected by temperature variations, which explains the significant influence of temperature on the pull-in voltage and on-state capacitance.
Abstract: The influence of temperature on electrical, mechanical and RF-performance of a BiCMOS embedded RF-MEMS switch has been demonstrated. Instead of exclusively estimating the temperature-dependent RF-MEMS switch key performance parameters, understanding the temperature influence on the mechanics together with the related electrical and RF-performance is preferred. A detailed thermo-mechanical analysis of the suspended membrane shows that the membrane shape and contact formation is strongly affected by temperature variations. It explains the significant influence of temperature on the pull-in voltage and on-state capacitance showing that a thermo-mechanical analysis is absolutely mandatory for an efficient process and design optimization to increase the temperature robustness.

Patent
23 Dec 2013
TL;DR: In this paper, a chip antenna comprising at least one emitter which extends parallel to a main surface of a semiconductor substrate supporting the chip antenna, where the emitter is arranged on an island-like support zone of the substrate, the support zone being surrounded by a trench which is completely filled with a gas.
Abstract: A chip antenna comprising at least one emitter which extends parallel to a main surface of a semiconductor substrate supporting the chip antenna, wherein the emitter is arranged on an island-like support zone of the semiconductor substrate, the support zone being surrounded by at least one trench which is completely filled with a gas, the trench passing through the entire depth of the semiconductor substrate and being bridged by at least one retaining web which forms a supporting connection between the support zone and the rest of the semiconductor substrate.

Proceedings ArticleDOI
28 Mar 2013
TL;DR: In this article, a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process, is presented.
Abstract: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process. All bits are digitally controlled. The 22.5° and 45° bits are based on switched low-pass network while the 90° and 180° bits are based on switching between high-pass/low-pass filters. Filters are implemented using on-chip spiral inductors and high-Q MIM capacitors. Switching functionality is obtained by isolated NMOS transistors employing resistive body floating technique. All bits are optimized to minimize the RMS phase error. Ordering of bits is optimized so as to minimize the overall insertion loss. Simulated insertion loss is 12±2 dB and RMS phase error is less than 2° over X-band frequencies.


Journal ArticleDOI
TL;DR: A novel failure investigation methodology dedicated to RF-MEMS capacitive switches based on a 250 nm BiCMOS BEOL technology, which facilitates the identification early failure detection, hence of the process yield.

Proceedings ArticleDOI
28 Mar 2013
TL;DR: In this paper, the authors present the building blocks of an X-band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays.
Abstract: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays. The T/R module consists of a T/R switch, two SPDT switches, a power amplifier, a low noise amplifier, a phase shifter and a variable gain amplifier (not presented). The T/R switch, SPDT switch and the phase shifter are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum insertion loss of 2.1 dB, an isolation of 42 dB and has an input PldB of 27.4 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band. The PA resulted in a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25 % PAE. The LNA has 1.65 dB noise figure (mean) with a gain more than 19 dB at X-Band. Lastly, the phase shifter achieves simulated RMS phase and gain errors of 1°-3.5° and 0.8-1.8 dB at X-Band.

Proceedings ArticleDOI
28 Mar 2013
TL;DR: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process, optimized to minimize the RMS phase error.
Abstract: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process. All bits are digitally controlled. The 22.5° and 45° bits are based on switched low-pass network while the 90° and 180° bits are based on switching between high-pass/low-pass filters. Filters are implemented using on-chip spiral inductors and high-Q MIM capacitors. Switching functionality is obtained by isolated NMOS transistors employing resistive body floating technique. All bits are optimized to minimize the RMS phase error. Ordering of bits is optimized so as to minimize the overall insertion loss. Simulated insertion loss is 12±2 dB and RMS phase error is less than 2° over X-band frequencies.

01 Jul 2013
TL;DR: In this paper, a phase shifter was implemented using IHP's MEMS switch embedded 0.25 μm SG25H1 SiGe BiCMOS technology for W band 77 GHz.
Abstract: 2 bit MEMS digital phase shifter has been implemented using IHP’s MEMS switch embedded 0.25 μm SG25H1 SiGe BiCMOS technology for W band 77 GHz The implemented phase shifter covers 0-67.5 with 22.5 phase increments in 4 states. Input/output impedances of all 4 states are matched below 14dB return loss with 8 GHz bandwidth. Maximum of 4 (RMS) phase error with insertion loss of 8.8 dB is measured at 77 GHz for 2 bit phase shifter. The fully BiCMOS embedded low-loss and small size MEMS switches enable an overall compact and low-loss phase shifter design.

Proceedings ArticleDOI
30 Sep 2013
TL;DR: In this paper, the authors present the building blocks of an X-band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays.
Abstract: This paper presents the building blocks of an X-Band T/R module in a 0.25 μm SiGe BiCMOS technology for phased arrays. The T/R module consists of a T/R switch, two SPDT switches, a power amplifier, a low noise amplifier, a phase shifter and a variable gain amplifier (not presented). The T/R switch, SPDT switch and the phase shifter are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum insertion loss of 2.1 dB, an isolation of 42 dB and has an input P1dB of 27.4 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band. The PA resulted in a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25 % PAE. The LNA has 1.65 dB noise figure (mean) with a gain more than 19 dB at X-Band. Lastly, the phase shifter achieves simulated RMS phase and gain errors of 1°-3.5° and 0.8-1.8 dB at X-Band.

Proceedings ArticleDOI
30 Sep 2013
TL;DR: In this article, a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process, is presented.
Abstract: This paper presents a 4-bit passive phase shifter for X-band (8-12 GHz) phased-arrays, implemented in 0.25-μm SiGe BiCMOS process. All bits are digitally controlled. The 22.5° and 45° bits are based on switched low-pass network while the 90° and 180° bits are based on switching between high-pass/low-pass filters. Filters are implemented using on-chip spiral inductors and high-Q MIM capacitors. Switching functionality is obtained by isolated NMOS transistors employing resistive body floating technique. All bits are optimized to minimize the RMS phase error. Ordering of bits is optimized so as to minimize the overall insertion loss. Simulated insertion loss is 12±2 dB and RMS phase error is less than 2° over X-band frequencies.