Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

Three-dimensional silicon integration

A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the static timing tool PathMill as its crosstalk extension (CTX). A comparison of simulation results between this approach and SPICE is also provided.

Deep sub-micron static timing analysis in presence of crosstalk

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

The circuit and physical design of the POWER4 microprocessor

A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

Constraint-based global router for routing high performance designs

A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock distribution networks corresponding to three microprocessor families are summarized. It is found that global clock interconnect performance and short-term jitter present the greatest challenges to the continued use of conventional clock distribution methodologies. An extrapolation of trends describing the percentage of clock period consumed by global skew and short-term jitter identifies the 32-nm technology generation of the 2002 International Technology Roadmap for Semiconductors (ITRS) as the first technology generation within which alternate methods of clock distribution may be warranted. Research efforts investigating interboard through intrachip optical clock distribution are also summarized. An optical distribution network compatible with high volume manufacturing in conjunction with a suitable means of providing optical-to-electrical signal conversion comprise the two fundamental challenges facing successful implementation of an optical clock distribution network. It is found that a global guided-wave distribution capable of efficient input and output coupling of optical power is required to meet the first challenge. The identification of a suitable means of optical-to-electrical conversion, however, remains an active topic of research.

Electrical and optical clock distribution networks for gigascale microprocessors

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

IBM POWER6 microprocessor physical design and design methodology

A program method for noise calculation and modeling caculates crosstalk voltage for a planned chip design, by first running routing and crosstalk routines for creating crosstalk rules for the planned design of a chip and loading crosstalk rules after routing is completed, and calculating the noise voltage of the planned design based on the exact topologies/paths of the victim and perpetrator nets of the planned design by path tracing and outputing a program file which contains the calculated noise voltage and a complete tabulation of the key physical and electrical parameters of the victim and perpetrator nets of the planned design, and then modeling using a network analysis program to selected nets of the design which exceed allowed noise limitations and obtaining the planned design net's network topology as an output while using the program file containing noise voltage calculation results as an input to the net's topology circuit simulation modeling program and outputting a nodal voltages vs. time data at each receiver location on a victim net as well as key nodes on any perpetrator nets of said planned design.

Calculating crosstalk voltage from IC craftsman routing data

A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements which can then be passed to a routing tool.

Method of on-chip interconnect design

An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Michael Alexander Bowen

Papers

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

IBM POWER6 microprocessor physical design and design methodology

Calculating crosstalk voltage from IC craftsman routing data

Method of on-chip interconnect design

Data processing system and method to estimate power in mixed dynamic/static CMOS designs