Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

Three-dimensional silicon integration

A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

ASYMMETRIC MESH NoC TOPOLOGIES

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Automatic construction of deadlock free interconnects

Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

Heterogeneous channel capacities in an interconnect

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping.

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

An automated method and apparatus for positioning gate array circuits in an integrated circuit design An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

IBM POWER6 microprocessor physical design and design methodology

A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew

A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations Physical design attributes can include coordinates and an orientation The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design

David W. Lewis

Papers

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

IBM POWER6 microprocessor physical design and design methodology

Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew

Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design