M
Michael Konow
Researcher at Intel
Publications - 9
Citations - 1234
Michael Konow is an academic researcher from Intel. The author has contributed to research in topics: Shared memory & Single-chip Cloud Computer. The author has an hindex of 7, co-authored 8 publications receiving 1213 citations.
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Proceedings ArticleDOI
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard,Saurabh Dighe,Yatin Hoskote,Sriram R. Vangal,D. Finan,G. Ruhl,David Jenkins,H. Wilson,Nitin Borkar,Gerhard Schrom,Fabrice Pailet,Shailendra Jain,Tiju Jacob,Satish Yada,Sravan K. Marella,Praveen Salihundam,Vasantha Erraguntla,Michael Konow,Michael Riepen,Guido Droege,Joerg Lindemann,Matthias Gries,Thomas Apel,Kersten Henriss,Tor Lund-Larsen,Sebastian Steibl,Shekhar Borkar,Vivek De,Rob F. Van der Wijngaart,Timothy G. Mattson +29 more
TL;DR: This paper presents a prototype chip that integrates 48 Pentium™ class IA-32 cores on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery to realize a data-center-on-a-die microprocessor architecture.
Journal ArticleDOI
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
Jason Howard,Saurabh Dighe,Sriram R. Vangal,G. Ruhl,Nitin Borkar,Shailendra Jain,Vasantha Erraguntla,Michael Konow,Michael Riepen,Matthias Gries,Guido Droege,Tor Lund-Larsen,Sebastian Steibl,S. Borkar,Vivek De,R Van Der Wijngaart +15 more
TL;DR: A multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture that uses message passing while exploiting 384 KB of on-die shared memory for fine grain power management.
Book ChapterDOI
RCKMPI - lightweight MPI implementation for intel's single-chip cloud computer (SCC)
TL;DR: This paper presents an MPI implementation (RCKMPI) that uses an efficient mix of MPB and DDR3 shared memory for low level communication that results in equal or lower transmission times than when communicating through the on die buffer alone.
Proceedings ArticleDOI
An FPGA-based Pentium® in a complete desktop system
TL;DR: This work uses a FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level 1 caches and experimented with interfacing hardware accelerators such as DES and AES engines which resulted in 27x speedups.
Journal ArticleDOI
SCC: A Flexible Architecture for Many-Core Platform Research
TL;DR: The Single-chip Cloud Computer (SCC) experimental processor by Intel Labs is a "concept vehicle" aimed at scaling future multicore processors and serving as a software research platform.