Michael Riepen

TL;DR: This paper presents a prototype chip that integrates 48 Pentium™ class IA-32 cores on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery to realize a data-center-on-a-die microprocessor architecture.

TL;DR: A multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture that uses message passing while exploiting 384 KB of on-die shared memory for fine grain power management.

TL;DR: The programmer's view of this chip is described and RCCE is described: the native message passing model created for the SCC processor, an intermediate case, sharing traits of message passing and shared memory architectures.

TL;DR: This paper presents an MPI implementation (RCKMPI) that uses an efficient mix of MPB and DDR3 shared memory for low level communication that results in equal or lower transmission times than when communicating through the on die buffer alone.

TL;DR: In this article, an idle removing block operating at a first clock speed to remove idles from received data stream, a buffer coupled to the idle removal control signal to enable the removal of idles by the idle removing blocks, and an idle insertion block coupled with the buffer to receive data stream from the buffer and insert idles into the data packets, the idle insertion blocks receiving an idle inserting control signal from a buffer to enable insertion of the idles.