For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

III-V nanowires (NWs) are promising for a wide range of applications, ranging from optics to electronics, energy, and biological sensing. The structural quality of NWs is of paramount importance for the performance of such future NW-based devices. Random structural defects and polytypism occur naturally in semiconductor NWs, but progress both on the theoretical understanding and experimental control have been achieved recently. Here, we review progress towards the realization of perfect wurtzite and zinc-blende phases in III-V NWs, eventually leading to true phase engineering in single NWs.

Crystal Phases in III--V Nanowires: From Random Toward Engineered Polytypism

An up-to-date literature overview on relevant approaches for controlling circuital characteristics and radiation properties of dielectric resonator antennas (DRAs) is presented The main advantages of DRAs are discussed in detail, while reviewing the most effective techniques for antenna feeding as well as for size reduction Furthermore, advanced design solutions for enhancing the realized gain of individual DRAs are investigated In this way, guidance is provided to radio frequency (RF) front-end designers in the selection of different antenna topologies useful to achieve the required antenna performance in terms of frequency response, gain, and polarization Particular attention is put in the analysis of the progress which is being made in the application of DRA technology at millimeter-wave frequencies

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Dielectric Resonator Antennas: Basic Concepts, Design Guidelines, and Recent Developments at Millimeter-Wave Frequencies

We report growth by molecular beam epitaxy and structural characterization of gallium-nucleated GaAs nanowires on silicon. The influences of growth temperature and V/III ratio are investigated and compared in the case of oxide-covered and oxide-free substrates. We demonstrate a precise positioning process for Ga-nucleated GaAs nanowires using a hole array in a dielectric layer thermally grown on silicon. Crystal quality is analyzed by high resolution transmission electron microscopy. Crystal structure evolves from pure zinc blende to pure wurtzite along a single nanowire, with a transition region.

https://iopscience.iop.org/article/10.1088/0957-4484/21/38/385602/pdf

Gold-free growth of GaAs nanowires on silicon: arrays and polytypism

Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in “ultimate” transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.

Vertical nanowire array-based field effect transistors for ultimate scaling

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

We present dc and RF characterization of InAs nanowire field-effect transistors (FETs) heterogeneously integrated on Si substrates in a geometry suitable for circuit applications. The FET consists of an array of 182 vertical InAs nanowires with about 6-nm HfO2 high-k gate dielectric and a wrap-gate length of 250 nm. The transistor has a transconductance of 155 mS/mm and an on-current of 550 mA/mm at a gate voltage of 1.5 V and a drain voltage of 1 V. S-parameter measurements yield an extrinsic cutoff frequency of 9.3 GHz and a extrinsic maximum oscillation frequency of 14.3 GHz.

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RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates

A readily mass-producible, flip-chip assembled, and slot-coupled III-V compound semiconductor dielectric resonator antenna operating in the millimeter-wave spectrum has been fabricated and characterized. The antenna has a 6.1% relative bandwidth, deduced from its 10 dB return loss over 58.8–62.5 GHz, located around the resonance at 60.5 GHz. Gating in the delay-domain alleviated the analysis of the complex response from the measured structure. The radiation efficiency is better than ${-}0.1$ dB in simulations fed from the on-chip coupling-structure, but reduced by 3.7 dB insertion loss through the measurement assembly feed. Antenna gain measurements show distortion in relation to the simulated pattern, which has a maximum gain of 6 dBi, mainly caused by interference from the electrically large connector used in the assembly. Mode degeneration in the utilized quadratic-footprint resonator was not seen to influence the performance of the antenna. The antenna is intended for on-chip integration and the fabrication technology allows scaling of the operation frequency over the complete millimeter-wave spectrum.

Slot-Coupled Millimeter-Wave Dielectric Resonator Antenna for High-Efficiency Monolithic Integration

We demonstrate the use of a GaAs-AlGaAs gated tunnel diode (GTD) in an ultra-wideband (UWB) wavelet generator. An inductor is integrated to form an oscillator circuit, which is driven by the negative differential conductance property of a GTD. It is demonstrated that as the gate tunes the magnitude of the output conductance, the oscillator may be switched on and off, creating short RF pulses. The shortest pulses generated are 500 ps long, the highest output power for the free running oscillator is -4.1 dBm, and the highest oscillation frequency is 22 GHz. Analytical expressions based on the van der Pol equation describing the pulse length and amplitude are presented. This technique is applicable for high frequency impulse radio UWB implementations.

20 GHz Wavelet Generator Using a Gated Tunnel Diode

The paper reports on the bias stabilization of a 60-GHz resonant-tunneling diode (RTD)-based oscillator operated in pulsed mode. The oscillator contains an on-chip stabilizing capacitor, enabling the minimum dc consumption possible for such an RTD oscillator to be obtained, since all of the dc current is consumed by the active device. This is achieved without imposing restraints on the output power or introducing parasitic oscillations in the bias network. The oscillator that was constructed produces short 75-ps wavelets at 60 GHz, at an energy consumption of 1.3 pJ, during generation of a pulse. Experimental, simulated, and analytical results are presented for demonstrating how this mode of operation can be utilized in negative differential conductance oscillators.

Mikael Egard

Papers

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates

Slot-Coupled Millimeter-Wave Dielectric Resonator Antenna for High-Efficiency Monolithic Integration

20 GHz Wavelet Generator Using a Gated Tunnel Diode

Bias Stabilization of Negative Differential Conductance Oscillators Operated in Pulsed Mode