For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

A III–V nanowire channel on silicon for high-performance vertical transistors

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.

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III–V compound semiconductor transistors—from planar to nanowire structures

III-V nanowires (NWs) are promising for a wide range of applications, ranging from optics to electronics, energy, and biological sensing. The structural quality of NWs is of paramount importance for the performance of such future NW-based devices. Random structural defects and polytypism occur naturally in semiconductor NWs, but progress both on the theoretical understanding and experimental control have been achieved recently. Here, we review progress towards the realization of perfect wurtzite and zinc-blende phases in III-V NWs, eventually leading to true phase engineering in single NWs.

Crystal Phases in III--V Nanowires: From Random Toward Engineered Polytypism

We report growth by molecular beam epitaxy and structural characterization of gallium-nucleated GaAs nanowires on silicon. The influences of growth temperature and V/III ratio are investigated and compared in the case of oxide-covered and oxide-free substrates. We demonstrate a precise positioning process for Ga-nucleated GaAs nanowires using a hole array in a dielectric layer thermally grown on silicon. Crystal quality is analyzed by high resolution transmission electron microscopy. Crystal structure evolves from pure zinc blende to pure wurtzite along a single nanowire, with a transition region.

https://iopscience.iop.org/article/10.1088/0957-4484/21/38/385602/pdf

Gold-free growth of GaAs nanowires on silicon: arrays and polytypism

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gate-all-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ~80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase in transconductance with frequency is explored in a very wide frequency range (1 Hz-70 GHz) and a distributed RC network is used to model the oxide and trap capacitances. An evaluation of vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-κ gate dielectric shows a deep border-trap density of about 1020cm-3eV-1 and a near-interfacial trap density of about 1021cm-3eV-1. The latter causes an almost steplike increase in transconductance at 1-10 GHz. This demonstrates the importance of high-frequency characterization of high-κ dielectrics in III-V MOSFETs.

/pdf/a-high-frequency-transconductance-method-for-4n08u5trm2.pdf

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

This paper presents dc and RF characterization as well as modeling of vertical InAs nanowire (NW) MOSFETs with LG=200 nm and Al2O3/HfO2 high-κ dielectric. Measurements at VDS=0.5 V show that high transconductance (gm=1.37 mS/μm), high drive current (IDS=1.34 mA/μm), and low ON-resistance (RON=287 Ωμm) can be realized using vertical InAs NWs on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, SVG·LG·WG, is determined to be lowered by one order of magnitude compared with similar devices with a high-κ film consisting of HfO2 only. In addition, with a virtual source model we are able to determine the intrinsic transport properties. These devices (LG=200 nm) show a high injection velocity (vinj=1.7×107 cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.

/pdf/extrinsic-and-intrinsic-performance-of-vertical-inas-4dclp51guo.pdf

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

Organ-on-chip systems are promising new in vitro research tools in medical, pharmaceutical, and biological research. Their main benefit, compared to standard cell culture platforms, lies in the improved in vivo resemblance of the cell culture environment. A critical aspect of these systems is the ability to monitor both the cell culture conditions and biological responses of the cultured cells, such as proliferation and differentiation rates, release of signaling molecules, and metabolic activity. Today, this is mostly done using microscopy techniques and off-chip analytical techniques and assays. Integrating in situ analysis methods on-chip enables improved time resolution, continuous measurements, and a faster read-out; hence, more information can be obtained from the developed organ and disease models. Integrated electrical, electrochemical, and optical sensors have been developed and used for chemical analysis in lab-on-a-chip systems for many years, and recently some of these sensing principles have started to find use in organ-on-chip systems as well. This perspective review describes the basic sensing principles, sensor fabrication, and sensor integration in organ-on-chip systems. The review also presents the current state of the art of integrated sensors and discusses future potential. We bring a technological perspective, with the aim of introducing in-line sensing and its promise to advance organ-on-chip systems and the challenges that lie in the integration to researchers without expertise in sensor technology.

Sofia Johansson

Papers

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

In-Line Analysis of Organ-on-Chip Systems with Sensors: Integration, Fabrication, Challenges, and Potential.