[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

This review article aims to provide an updated and comprehensive description of the development of the Electric Current Activated/assisted Sintering technique (ECAS) for the obtainment of dense materials including nanostructured ones. The use of ECAS for pure sintering purposes, when starting from already synthesized powders promoters, and to obtain the desired material by simultaneously performing synthesis and consolidation in one-step is reviewed. Specifically, more than a thousand papers published on this subject during the past decades are taken into account. The experimental procedures, formation mechanisms, characteristics, and functionality of a wide spectrum of dense materials fabricated by ECAS are presented. The influence of the most important operating parameters (i.e. current intensity, temperature, processing time, etc.) on product characteristics and process dynamics is reviewed for a large family of materials including ceramics, intermetallics, metal–ceramic and ceramic–ceramic composites. In this review, systems where synthesis and densification stages occur simultaneously, i.e. a fully dense product is formed immediately after reaction completion, as well as those ones for which a satisfactory densification degree is reached only by maintaining the application of the electric current once the full reaction conversion is obtained, are identified. In addition, emphasis is given to the obtainment of nanostructured dense materials due to their rapid progress and wide applications. Specifically, the effect of mechanical activation by ball milling of starting powders on ECAS process dynamics and product characteristics (i.e. density and microstructure) is analysed. The emerging theme from the large majority of the reviewed investigations is the comparison of ECAS over conventional methods including pressureless sintering, hot pressing, and others. Theoretical analysis pertaining to such technique is also proposed following the last results obtained on this topic.

Consolidation/synthesis of materials by electric current activated/assisted sintering

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Hydrogen evolution reaction (HER) in alkaline medium is currently a point of focus for sustainable development of hydrogen as an alternative clean fuel for various energy systems, but suffers from sluggish reaction kinetics due to additional water dissociation step. So, the state-of-the-art catalysts performing well in acidic media lose considerable catalytic performance in alkaline media. This review summarizes the recent developments to overcome the kinetics issues of alkaline HER, synthesis of materials with modified morphologies, and electronic structures to tune the active sites and their applications as efficient catalysts for HER. It first explains the fundamentals and electrochemistry of HER and then outlines the requirements for an efficient and stable catalyst in alkaline medium. The challenges with alkaline HER and limitation with the electrocatalysts along with prospective solutions are then highlighted. It further describes the synthesis methods of advanced nanostructures based on carbon, noble, and inexpensive metals and their heterogeneous structures. These heterogeneous structures provide some ideal systems for analyzing the role of structure and synergy on alkaline HER catalysis. At the end, it provides the concluding remarks and future perspectives that can be helpful for tuning the catalysts active-sites with improved electrochemical efficiencies in future.

https://onlinelibrary.wiley.com/doi/pdf/10.1002/advs.201700464

Electrocatalysts for Hydrogen Evolution in Alkaline Electrolytes: Mechanisms, Challenges, and Prospective Solutions

Hybrid supercapacitors with their improved performance in energy density without altering their power density have been in trend since recent years. The hybrid supercapacitor delivers higher specific capacitance in comparison to the existing electric double layer capacitor (EDLC) and pseudocapacitors. Generally, the asymmetric behavior of hybrid supercapacitors which is the combination of EDLC and pseudocapacitor acts as an enhancer in its respective capacitance values. This asymmetric approach marks a new beginning towards the much-needed pollution free, long lasting and proficient energy-storing performance. Corresponding to their utilization in hybrid electric vehicles and similar sort of power necessity based devices; the research in developing new advanced storage devices finds an enormous and vast future ahead. The most significant factor for the energy efficient applications demands a considerably higher ratio of surface to the volume by incorporation of new materials. This review article gives an overview of recent advances in the development of hybrid supercapacitors, storage mechanism, criteria of formation, components, different electrode and electrolyte materials, electrochemical profile assessment, design fabrication and their applications.

A review on recent advances in hybrid supercapacitors: Design, fabrication and applications

Micro Cu/Sn copper pillar bumps, with excellent conductivity and thermal conductivity, show broad prospects in electronic packaging. It is of significance to study the impact of aging temperature and time on the intermetallic reaction in micro copper pillar bump. This pager concentrates on the influence of different aging temperature and time on the intermetallic reaction in 15μm micro copper pillar bumps. The bumps are prepared to be annealed for different time at different temperature. We find that the increase of aging time and temperature will significantly promote the morphology change and growth of IMCs, which are key to the reliability of micro Cu/Sn copper pillar bumps. The interface morphology changes from scallop-shaped to relatively flat after aging. The growth of Cu6Sn5 is determined by the production by Cu/Sn and the consumption of Cu3Sn.

Influence of aging temperature and time on the intermetallic reaction in 15μm Cu/Sn copper pillar bump

Material loss, especially in metal and 2D materials, is the bottleneck for high‐performance integrated optical devices. Here, a novel concept by utilizing the high‐loss materials in a non‐Hermitian system instead of avoiding the loss materials. It is theoretically analyzed how the complex refractive index affects the loss of optical devices based on a two‐waveguide‐coupled non‐Hermitian system. The results reveal that the loss of optical devices can be improved by increasing the loss of materials or the difference in real refractive indexes. It is experimentally verified that a high loss material can be placed close to the optical waveguide without introducing non‐negligible loss to the optical devices, by demonstrating a thermo‐optic phase shifter with a metallic heater placed very close to the silicon waveguide. As a result, the insertion loss is only 0.1 dB for the 100 μm long heater with a gap of 400 nm, and the largest bandwidth for the metallic heater reaches up to 280 kHz. The finding offers a way to realize high‐performance optical devices with high‐loss materials, contributing to the practical applications of strongly absorbing materials based on non‐Hermitian optics.

Strategy for Low‐Loss Optical Devices When Using High‐Loss Materials

In recent years, silver alloy wire has been widely used in semiconductor industry. In contrast to conventional gold wire, silver alloy wire has better electrical property, thermal conductivity and lower cost while tends to migrate more easily under high temperature and current density. In this paper, electro-migration (EM) of silver alloy wire after wire bonding has been studied. Under accelerated test, cracks forms not only on silver alloy wire surface but also in silver alloy wire while gold wire remain the same. Silver ion not only migrates on the wire surface also inside the wire. Temperature and current density both accelerate the EM. The conclusion could be a reference for further gold reduction of Au/Ag alloy wire in semiconductor bonding.

Electro-migration of silver alloy wire with its application on bonding

Electroless Sn films have great potential in the lead-free age such as for high-density, fine-pitch, narrow soldering pad and bump interconnection applications. In the present work, electroless Sn were deposited onto lead-frame alloys (C194 and FeNi42). The microstructures of the electroless Sn films and tin whisker growth in thermal / humiditive chamber were investigated with scanning electron microscope and optical metallography. It was found that, in comparison with the FeNi42 substrate, the C194 substrate was more favorable for the deposition of electroless Sn coatings. The grain size increased with increase of the thickness of the Sn deposits. Within 45 min, autocatalytic activity still exists, which could keep the autocatalytic deposition of electroless tin on the C194 substrate. Tin whiskers growth was found only after 1000-hour exposure of the samples to the thermal-humiditive environment.

Tin whisker formation on electroless tin films deposited on lead-frame alloys

3D NAND flash memory has become a state-of-the-art technology of non-volatile memory. Different from planar 2D NAND flash memory, polysilicon channel is adopted by 3D NAND flash memory. Because of grain boundaries, device suffers from significant performance variation. This work investigates the effect of grain boundary on MONOS-structured NAND flash memory performance by TCAD simulation. The variability of electrical performance was demonstrated under random grain boundary structure. To further understand the grain boundary effect on device performance, grain size, grain boundary position and grain boundary angle was investigated. When grain size is smaller than gate length, it shows a larger threshold voltage variation. When grain size is big enough, the position of grain boundary matters. When grain boundary locates right below the middle of the gate, threshold voltage shifts the most. Moreover, comparing to vertical grain boundaries, the threshold voltage shifts up for grain boundaries in parallel to channel. This work includes a comprehensive study about the effect of grain boundary on 3D NAND flash memory performance. It could be used for the optimization of polysilicon process technology.

Ming Li

Papers

Influence of aging temperature and time on the intermetallic reaction in 15μm Cu/Sn copper pillar bump

Strategy for Low‐Loss Optical Devices When Using High‐Loss Materials

Electro-migration of silver alloy wire with its application on bonding

Tin whisker formation on electroless tin films deposited on lead-frame alloys

Investigation of Grain Boundaries Effect on 3D NAND Flash by TCAD Simulation