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Design Of Analog Cmos Integrated Circuits

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Integration of the whole mode-locked laser onto a single piece of semiconductor offers a number of advantages, including total elimination of optical alignment processes, improved mechanical stability, and the generation of short optical pulses at much higher repetition frequencies. Semiconductor laser processing technologies were used to implement the colliding-pulse mode-locking (CPM) scheme, which is known to effectively shorten the pulses and increase stability, on a miniature monolithic semiconductor cavity. The principles of and recent progress in monolithic CPM quantum-well lasers are reviewed. >

Monolithic colliding-pulse mode-locked quantum well lasers

A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-?m CMOS process to supply 1.21 V to a load ranging from 1 ?A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.

http://wordpress.nmsu.edu/pfurth/files/2015/06/RNMCCB_LDO_TCASII_2010.pdf

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A new tri-level switching method for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed switching method enhances the efficiency of digital-to-analogue converter switching energy by 93.7% and achieves a 75% reduction in the total capacitor size, compared with the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC has no dependency on the accuracy of the mid-level reference voltage (V cm) except in the least significant bit, and the common-mode voltage at the input of the comparator will remain approximately unchanged. Analytical calculations and behavioural simulation results are provided to demonstrate the effectiveness of the proposed switching scheme.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.3451

Energy-efficient high-accuracy switching method for SAR ADCs

This paper presents a digital blind background calibration technique of imperfections in time-interleaved analog-to-digital converters (TI-ADCs). The proposed technique directly operates on the statistics of the input signal to continuously estimate and eliminate the conversion errors resulted from offset, gain, and timing mismatch. Behavioral simulations are presented for a 4-channel 10-bit TI-ADC in order to verify the effectiveness of the proposed method. The signal-to-noise-and-distortion ratio (SNDR) is enhanced from 33.7 dB to more than 61 dB using the introduced calibration technique. This calibration method converges after roughly $4 \times 10^{6}$ conversions.

Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

Hybrid Cascode Compensation for Two-Stage CMOS Opamps

The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched-capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided.

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

This brief presents a capacitor switching technique to reduce the power consumption in successive approximation register (SAR) analog-to-digital converters (ADCs). The proposed method ideally does not consume any switching energy in digital-to-analog converter and for a 10-bit ADC; it achieves 87% reduction in the total capacitor area compared to the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC does not depend on the accuracy of the mid-level reference voltage ( $ {V}_{\text{cm}}$ ). Moreover, the common-mode input voltage of the comparator will remain constant. The proposed ADC is simulated in a 90-nm CMOS technology with sampling rate of 100 kS/s and resolution of 10-bit. The simulation results achieve an 8.5 effective number of bits with about 0.5- ${\mu }\text{W}$ power consumption resulting in a FoM of 9.76 fJ/conversion-step.

Mohammad Yavari

Papers

Energy-efficient high-accuracy switching method for SAR ADCs

Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs

Hybrid Cascode Compensation for Two-Stage CMOS Opamps

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

An Energy-Efficient DAC Switching Method for SAR ADCs