Memristor-enabled neuromorphic computing systems provide a fast and energy-efficient approach to training neural networks1–4. However, convolutional neural networks (CNNs)—one of the most important models for image recognition5—have not yet been fully hardware-implemented using memristor crossbars, which are cross-point arrays with a memristor device at each intersection. Moreover, achieving software-comparable results is highly challenging owing to the poor yield, large variation and other non-ideal characteristics of devices6–9. Here we report the fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs, which integrate eight 2,048-cell memristor arrays to improve parallel-computing efficiency. In addition, we propose an effective hybrid-training method to adapt to device imperfections and improve the overall system performance. We built a five-layer memristor-based CNN to perform MNIST10 image recognition, and achieved a high accuracy of more than 96 per cent. In addition to parallel convolutions using different kernels with shared inputs, replication of multiple identical kernels in memristor arrays was demonstrated for processing different inputs in parallel. The memristor-based CNN neuromorphic system has an energy efficiency more than two orders of magnitude greater than that of state-of-the-art graphics-processing units, and is shown to be scalable to larger networks, such as residual neural networks. Our results are expected to enable a viable memristor-based non-von Neumann hardware solution for deep neural networks and edge computing. A fully hardware-based memristor convolutional neural network using a hybrid training method achieves an energy efficiency more than two orders of magnitude greater than that of graphics-processing units.

Fully hardware-implemented memristor convolutional neural network

This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today’s von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc. Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuro-inspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy). Finally, we give an outlook on the customization of the learning algorithms for efficient hardware implementation.

Neuro-Inspired Computing With Emerging Nonvolatile Memorys

The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar / pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (P r ) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark on-chip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.

Ferroelectric FET analog synapse for acceleration of deep neural network training

Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the “analog” emerging nonvolatile memory (eNVM)’s “nonideal” device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification.

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Neuromorphic computing is a promising alternative to conventional computing systems as it could enable parallel computation and adaptive learning process. However, the development of energy efficient neuromorphic hardware systems has been hindered by the limited performance of analog synaptic devices. Here, we demonstrate the analog conductance modulation behavior in the ferroelectric thin-film transistors (FeTFT) that have the nanoscale ferroelectric material and oxide semiconductors. Accurate control of polarization changes in the nanoscale ferroelectric layer induces conductance modulation to demonstrate linear potentiation and depression characteristics of FeTFTs. Our devices show potentiation and depression properties, including high linearity, multiple states, and small cycle-to-cycle/device-to-device variations. In simulations with measured properties, a neuromorphic system with FeTFT achieves 91.1% recognition accuracy of handwritten digits. This work may provide a way to realize the neuromorphic hardware systems that use FeTFTs as the synaptic devices.

Ferroelectric Analog Synaptic Transistors

We analyze the response of identical pulses on a filamentary resistive memory (RRAM) to implement the synapse function in neuromorphic systems. Our findings show that the multilevel states of conductance are achieved by varying the measurement conditions related to the formation and rupture of a conductive filament. Furthermore, abrupt set switching behavior in the RRAM leads to an unchanged conductance state, leading to degradation in the accuracy of pattern recognition. Thus, we demonstrate a linear potentiation (or depression) behavior of conductance under identical pulses using the effect of barrier layer on the switching, which was realized by fabricating an RRAM on top of an Al electrode. As a result, when the range of the conductance is symmetrically controlled at both polarities, a significantly improved accuracy is achieved for pattern recognition using a neural network with a multilayer perceptron.

Improved Synaptic Behavior Under Identical Pulses Using AlO x /HfO 2 Bilayer RRAM Array for Neuromorphic Systems

We perform a comparative study of HfO2 and Ta2O5 resistive switching memory (RRAM) devices for their possible application as electronic synapses. By means of electrical characterization and simulations, we link their electrical behavior (digital or analog switching) to the properties and evolution of the conductive filament (CF). More specifically, we identify that bias-polarity-dependent digital switching in HfO2 RRAM is primarily related to the creation and rupture of an oxide barrier. Conversely, the modulation of the CF size in Ta2O5 RRAM allows bias-polarity-independent analog switching with multiple states. Therefore, when the Ta2O5 RRAM is used to implement a synapse in multilayer perceptron neural networks operated by back-propagation algorithms, patterns in handwritten digits can be recognized with high accuracy.

Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications

We demonstrate ultra-thin ALD-processed dual-oxide (Al 2 O 3 /TiO 2 ) hybrid device with memory and selector characteristics by engineering the stability of metal filament in Al 2 O 3 and TiO 2 layer. The optimized hybrid memory device shows outstanding performances such as low off current $( , low reset current $( , and high on/off ratio $(> 10^{4})$ . Inserting a Ti buffer layer which has a low electrode potential value, we observed excellent uniformity and retention property. Finally, an outstanding read/write margins and ultra-low power consumption are confirmed through array simulations of the proposed hybrid memory device.

Myounghun Kwak

Papers

Improved Synaptic Behavior Under Identical Pulses Using AlO x /HfO 2 Bilayer RRAM Array for Neuromorphic Systems

Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications

Ultra-thin 2 O 3 /TiO 2 ) Hybrid Device (Memory/Selector) with Extremely Low I off reset <1nA) for 3D Storage Class Memory