Showing papers by "Naresh R. Shanbhag published in 2006"

A 640-Mb/s 2048-bit programmable LDPC decoder chip

Abstract: A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.

Sequential Element Design With Built-In Soft Error Resilience

Abstract: This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

Soft-Error-Rate-Analysis (SERA) Methodology

Abstract: We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-mum CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 mum

Energy-efficient soft error-tolerant digital signal processing

Abstract: In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques - spatial, temporal and spatio-temporal- are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to P/sub er/=10/sup -2/ and P/sub er/=10/sup -3/ in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNR/sub des/=25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.

An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links

Abstract: A maximum-likelihood sequence estimation (MLSE) receiver is fabricated to combat dispersion/intersymbol interference (chromatic and polarization mode), noise (optical and electrical), and nonlinearities (e.g., fiber, receiver photodiode, or laser) in OC-192 metro and long-haul links. The MLSE receiver includes a variable gain amplifier with 40-dB gain range and 7.5-GHz 3-dB bandwidth, a 12.5-Gb/s 4-bit analog-to-digital converter, a dispersion-tolerant phase-locked loop, a 1:8 demultiplexer, and a digital equalizer implementing the MLSE algorithm. The MLSE receiver achieves more than 50% reach extension at signal-to-noise levels of interest as compared to conventional clock data recovery systems

Energy-efficient motion estimation using error-tolerance

Abstract: Presented is an energy-efficient motion estimation architecture using error-tolerance. The technique employs overscaling of the supply voltage (voltage overscaling (VOS)) to reduce power at the expense of timing errors, which are then corrected using algorithmic noise-tolerance (ANT) techniques. Referred to as input subsampled replica ANT (ISR-ANT), the proposed technique incorporates an input subsampled replica of the main sum of absolute difference (MSAD) block for obtaining the motion vectors in the presence of errors induced by VOS. Simulations show that the proposed technique can save up to 60% power over an optimal error-free present day system in a 130nm CMOS technology. Power savings increase to 79% in a 45nm predictive process technology.

An MLSE receiver for electronic-dispersion compensation of OC-192 fiber links

Abstract: A 9.953 to 12.5Gb/s MLSE receiver consisting of an AFE IC in a 0.18mum 3.3V ft=75GHz, and a digital IC in a 0.13pm 1.2V CMOS is presented. The AFE IC features a 7.5GHz 40dB VGA, a 4b 12.5GS/S ADC, a dispersion-tolerant clock-recovery unit, and a 1:8 DEMUX. The digital IC implements an 8-parallel, delayed recursion MLSE architecture and a nonlinear channel estimator. The 4.5W receiver meets the SONET jitter specifications with 2200ps/nm of dispersion at BER=104

Pattern-dependent phase detector for clock recovery

Abstract: A phase detector apparatus and method (200) used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator (206), where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transition from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments, the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance

Abstract: Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of 1rarr0 and 0rarr1, respectively. We study inverter chain circuits as well as sum-of-products implementation of random logic circuits in a typical 0.18-mum process under the influence of radiation induced soft errors. We quantify the SET tolerance of the proposed technique by using an error map and a recently developed tool soft-error rate analyzer (SERA). The results show that the DSFF incurs no speed penalty, if no SETs have reached the input of DSFF. Otherwise, the DSFF alone eliminates the 1rarr0 SETs while incurring a worst case speed and power penalty of 310 ps and 39 muW, respectively. The SCMOS eliminates the 0rarr1 SETs when the skewing factor is greater than four. Thus, the proposed technique potentially eliminates the impact of SETs with both polarities

Noise tolerant voltage controlled oscillator

Abstract: A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.

An Architectural Comparison of Reed-Solomon Soft-Decoding Algorithms

Abstract: Reed-Solomon codes are used as error-correcting codes in diverse communication system applications The decoding ing performance of traditional hard-decision Reed-Solomon decoders can be improved via the use of soft-decoding algorithms such as generalized minimum distance decoding, algebraic soft-decision decoding, and ordered statistics decoding While it is relatively straight-forward to compare the decoding performance of these algorithms, it is harder to compare their hardware complexity This is because an efficient architecture has a dramatic effect on the final implementation complexity In this paper, we present efficient hardware architectures for each of the soft-decoding algorithms and compare their implementation complexity