On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

저작근 근전도에 관한 정상교합자와 ii급 부정교합자의 비교 연구

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Razor: a low-power pipeline based on circuit-level timing speculation

Presented in this paper are low-power, reconfigurable adaptive CDMA multiuser receiver architectures developed via dynamic algorithmic transforms (DAT). The architectures achieve low-power operation via run-time reconfiguration of receiver complexity to match the requirements of a time-varying multiuser channel. Simulation results with 0.25 /spl mu/m, 2.3 V CMOS technology parameters indicate that the proposed architectures have high resistance to the near-far problem, and can achieve up to 60.4% in power savings compared to architectures without DAT depending on the interference situation.

Low-power CDMA multiuser receiver architectures

Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. The serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VOS) and reduced-precision replica (RPR) are applied to the decoder. By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.

/pdf/low-power-implementation-of-a-high-throughput-ldpc-decoder-3tyii0o17k.pdf

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Modern state-of-the-art I/O links today rely exclusively upon a high SNR channel and an equalization-based inner transceiver to achieve a BER of 10-15. The equalizer typically consists of a transmit pre-emphasis driver for pre-cursor equalization and a receive DFE for post-cursor cancellation. Recently, forward error-correction (FEC) coding has been proposed to improve the BER and reduce power in high-speed I/O links. However, error-propagation in the DFE is a significant issue affecting code performance. The link performance is also tied to FEC implementation parameters like degree of parallelism. This paper presents a framework for analyzing the impact of DFE burst errors and implementation parameters on end-to-end link performance. For 10.3125Gb/s transmission through a channel with 19dB loss at Nyquist rate and serial FEC implementation, we find that a code rate r = 0.8 gives the best ISI penalty vs coding gain trade-off, and a codeword length of 750 bits is necessary to meet target performance. Further, it is observed that the performance of burst error correction codes does not necessarily improve with codeword length, i.e., there is an BER-optimal block length at a given code rate.

/pdf/impact-of-dfe-error-propagation-on-fec-based-high-speed-i-o-56ee1k433w.pdf

Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links

Presented in this paper is a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high capacitance busses where the extra power dissipation due to the encoder and the decoder circuitry is offset by the power savings at the bus. A framework to characterize low-power encoding schemes is developed based upon the source-channel coding view. In this framework, a data source (characterized in a probabilistic manner) is passed through a decorrelating function f/sub 1/ first. Next, a variant of entropy coding function f/sub 2/ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f/sub 1/ and f/sub 2/ are proposed. Simulation results with an encoding scheme for data busses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/bit in 1.2 /spl mu/ CMOS technology and eight times more pourer savings compared to existing schemes with a typical value for bus capacitance of 50p F/bit. Simulation results with an encoding scheme for instruction address busses indicate an average reduction in transition activity by a factor of 3 times and 1.5 times over the Gray and TO coding schemes respectively.

/pdf/coding-for-low-power-address-and-data-busses-a-source-coding-4sfjqf01g0.pdf

Coding for low-power address and data busses: a source-coding framework and applications

Presented in this paper is a low-power technique, denoted as MIMO-AEC, to reduce energy dissipation in multi-input-multi-output (MIMO) signal processing systems. The proposed technique extends a previously proposed adaptive error-cancellation (AEC) technique to MIMO systems by employing an algorithm transformation denoted as MIMO-DECOR. The purpose of MIMO-DECOR is to reduce complexity by exploiting correlations inherent in MIMO systems, thereby improving the effectiveness of AEC. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results demonstrate 44.3% - 25.2% overhead reduction due to MIMO-DECOR and 69.1% - 64.2% energy savings over conventional implementations with no loss in algorithmic performance.

/pdf/low-power-aec-based-mimo-signal-processing-for-gigabit-12xsmwouyc.pdf

Naresh R. Shanbhag

Papers

Low-power CDMA multiuser receiver architectures

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links

Coding for low-power address and data busses: a source-coding framework and applications

Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers