On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

저작근 근전도에 관한 정상교합자와 ii급 부정교합자의 비교 연구

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Razor: a low-power pipeline based on circuit-level timing speculation

Deep In-memory Architectures for Machine Learning

The set of all polynomials vanishing on the imaginary axis in a polytope of polynomials is determined. This constitutes a significant step towards finding the boundary of stability in a polytope. >

On the partition of unstable standard polytopes of polynomials

Deep neural networks have achieved state-of-the art performance on various computer vision tasks. However, their deployment on resource-constrained devices has been hindered due to their high computational and storage complexity. While various complexity reduction techniques, such as lightweight network architecture design and parameter quantization, have been successful in reducing the cost of implementing these networks, these methods have often been considered orthogonal. In reality, existing quantization techniques fail to replicate their success on lightweight architectures such as MobileNet. To this end, we present a novel fully differentiable non-uniform quantizer that can be seamlessly mapped onto efficient ternary-based dot product engines. We conduct comprehensive experiments on CIFAR-10, ImageNet, and Visual Wake Words datasets. The proposed quantizer (DBQ) successfully tackles the daunting task of aggressively quantizing lightweight networks such as MobileNetV1, MobileNetV2, and ShuffleNetV2. DBQ achieves state-of-the art results with minimal training overhead and provides the best (pareto-optimal) accuracy-complexity trade-off.

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks

In this paper, we present an algorithmic noise tolerance (ANT) technique for low-power digital signal processing systems. The proposed technique employs a low-complexity forward-backward predictor to correct errors in a main DSP (MDSP) block due to voltage overscaling, which is an ultra low-voltage operating condition. For a frequency selective FIR filtering, it is shown that the proposed technique achieves up to 43% power savings over an optimally voltage scaled MDSP with a 5% area overhead.

A novel forward-backward predictor based low-power DSP system

We have recently proposed the concept of soft N-modular redundancy (soft NMR) [1] in order to design robust and energy-efficient computing systems in nanoscale processes, where soft NMR was shown to achieve orders-of-magnitude improvement in robustness with significant power savings over NMR. In this paper, we analyze the performance of soft NMR and compare it with that of NMR and algorithmic noise-tolerance (ANT). An 8-b multiplier and a DCT-based still image compression system in a commercial 45nm CMOS process is considered. Two metrics of system performance: system reliability P e,sys , and signal-to-noise ratio (SNR) are analyzed. We show that soft NMR always outperforms NMR and that our analysis predicts P e,sys and SNR to within 4.2% and 2.7dB on average, respectively, of the results of Monte Carlo simulations.

Naresh R. Shanbhag

Papers

Deep In-memory Architectures for Machine Learning

On the partition of unstable standard polytopes of polynomials

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks

A novel forward-backward predictor based low-power DSP system

Soft NMR: Analysis & application to DSP systems